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2 Commits
Author SHA1 Message Date
leonarski_f ec7278bd44 HLS: Changes to allow cosimulation with Vitis HLS 2023-10-18 14:44:30 +02:00
leonarski_f 98fe70315b FPGA: add bitshuffle to HLS modules (don't integrate at the moment into the whole design) 2023-09-30 11:28:01 +02:00