Add AzimuthalIntegrationSettings::ForceCPUinFPGAWorkflow so the FPGA
data-acquisition path can compute azimuthal integration on the CPU instead
of the FPGA. This removes the FPGA bin-count limit (FPGA_INTEGRATION_BIN_COUNT)
and adds per-bin standard deviation.
- MXAnalysisAfterFPGA runs AzIntEngineCPU on the assembled image; the FPGA
integration-map load and per-module read-back are skipped when forced.
- JFJochReceiverFPGA rejects bin counts above the FPGA limit at acquisition
start (unless CPU is forced) with an actionable error.
- Wire force_cpu through the broker (both directions) and the frontend.
Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
leonarski_fandClaude Opus 4.8