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Update receiver/README.md

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leonarski_f
2023-05-31 11:47:49 +02:00
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receiver/README.md
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@@ -44,52 +44,53 @@ To test that FPGA board is working properly without access to a JUNGFRAU detecto
## FPGA reference
FPGA setup can be done via 32-bit registers:
| Address | Bits | Meaning | Mode | Notes |
|-------------------|------|-----------------------------------------------------------------------|:-----|-----------------------------------|
| 0x00000 - 0x0FFFF | | Reserved for internal memory of MicroBlaze | | |
| 0x10000 | 32 | Action Control Register | | |
| | | Bit 0 - Action start | R/W | |
| | | Bit 1 - Action idle | R | |
| | | Bit 2 - Action cancel | R/W | cleared on reset or action start |
| | | Bit 12 - HBM catastrophic temp. error | R | |
| | | Bit 13 - HBM catastrophic temp. error | R | cleared on reset or action start |
| | | Bit 14 - HBM setup complete | R | |
| | | Bit 16 - AXI Mailbox interrupt 0 | R | |
| | | Bit 17 - AXI Mailbox interrupt 1 | R | |
| | | Bits 24-27 - Various errors in host memory writer | R | cleared on reset or action start |
| 0x10004 | 32 | Reserved | - | |
| 0x10008 | 32 | Set user LED G0 (yellow or green), 1 is on, 0 is off | R/W | |
| 0x1000C | 32 | Action GIT SHA1 | R | |
| 0x10010 | 32 | Action Type | R | |
| 0x10014 | 32 | Action Release Level | R | |
| 0x10018 | 32 | HBM current temperature | R | |
| 0x1001C | 32 | HBM max. temperature | R | reset on action start |
| 0x10020 | 32 | Max. number supported detector modules | R | constant |
| 0x10024 | 32 | Number of modules in internal packet generator memory | R | constant |
| 0x10028 | 64 | Pipeline stalls before writing to host memory | R | reset on action start |
| 0x10030 | 64 | Pipeline stalls before accessing HBM | R | reset on action start |
| 0x10038 | 32 | FIFO status (see action_config.v for details) | R/W | |
| 0x1003C | 32 | Reserved | - | |
| 0x10040 | 64 | Packets processed by the action | R/W | cleared on reset or action start |
| 0x10048 | 64 | Valid ethernet packets | R/W | cleared on reset |
| 0x10050 | 64 | Valid ICMP packets | R/W | cleared on reset |
| 0x10058 | 64 | Valid UDP packets | R/W | cleared on reset |
| 0x10060 | 64 | MAC address of FPGA card | R/W | network byte order |
| 0x10068 | 32 | IPv4 address of FPGA card | R/W | network byte order |
| 0x1006C | 32 | Number of detector modules | R/W | |
| 0x10070 | 32 | Data collection mode | R/W | |
| 0x10074 | 32 | One over energy in keV (in fixed-point:12 int. + 24 frac. bit format) | R/W | |
| 0x10078 | 32 | Number of frames to be generated by internal packet generator | R/W | |
| 0x1007C | 32 | Number of storage cells | R/W | |
| | | | | |
| 0x20000 - 0x2FFFF | | CMAC 100G | | See Xilinx PG203 for register map |
| 0x30000 - 0x3FFFF | | AXI Mailbox for Work Request / Work Completion | | See Xilinx PG114 for register map |
| 0x40000 - 0x4FFFF | | QuadSPI flash | | See Xilinx PG153 for register map |
| 0x60000 - 0x60FFF | 64 | Input calibration memory addresses block RAM | | |
| 0x70000 - 0x7FFFF | | AXI Firewall | | See Xilinx PG293 for register map |
| 0x80000 - 0x8FFFF | | Interrupt controller | | See Xilinx PG099 for register map |
| 0x70000 - 0x7FFFF | | PCIe DMA control | | See Xilinx PG195 for register map |
| 0xC0000 - 0xFFFFF | | Xilinx Card Management Solution Subsystem management subsystem | | See Xilinx PG348 for register map |
| Address | Bits | Meaning | Mode | Notes |
|-------------------|------|------------------------------------------------------------------------------------------------------|:-----|-----------------------------------|
| 0x00000 - 0x0FFFF | | Reserved for internal memory of MicroBlaze | | |
| 0x10000 | 32 | Action Control Register | | |
| | | Bit 0 - Action start | R/W | |
| | | Bit 1 - Action idle | R | |
| | | Bit 2 - Action cancel | R/W | cleared on reset or action start |
| | | Bit 3 - Clear network counters | R/W | cleared on reset or action start |
| | | Bit 4 - Host writer idle | R | cleared on reset |
| | | Bit 7 - Design number | R | 0 = PCIe #0, 1 = PCIe #1 |
| | | Bit 16 - AXI Mailbox interrupt 0 | R | |
| | | Bit 17 - AXI Mailbox interrupt 1 | R | |
| | | Bits 24-27 - Various errors in host memory writer | R | cleared on reset or action start |
| 0x10004 | 32 | Reserved | - | |
| 0x1000C | 32 | Action GIT SHA1 | R | |
| 0x10010 | 32 | Action Type | R | |
| 0x10014 | 32 | Action Release Level | R | |
| 0x10020 | 32 | Max. number supported detector modules | R | constant |
| 0x10024 | 32 | Number of modules in internal packet generator memory | R | constant |
| 0x10028 | 64 | Pipeline stalls before writing to host memory | R | reset on action start |
| 0x10030 | 64 | Pipeline stalls before accessing HBM | R | reset on action start |
| 0x10038 | 32 | FIFO status (see action_config.v for details) | R/W | |
| 0x1003C | 32 | Reserved | - | |
| 0x10040 | 64 | Packets processed by the action | R/W | cleared on reset or action start |
| 0x10048 | 64 | Valid ethernet packets | R/W | cleared on reset |
| 0x10050 | 64 | Valid ICMP packets | R/W | cleared on reset |
| 0x10058 | 64 | Valid UDP packets | R/W | cleared on reset |
| 0x10060 | 64 | MAC address of FPGA card | R/W | network byte order |
| 0x10068 | 32 | IPv4 address of FPGA card | R/W | network byte order |
| 0x1006C | 32 | Number of detector modules | R/W | |
| 0x10070 | 32 | Data collection mode | R/W | |
| | | Bit 0 - Conversion to photons | | |
| | | Bit 1 - Use internal packet generator | | |
| | | Bit 2 - Nonblocking operation (host writer will ignore frames if there is no available work request) | | |
| | | Bit 16:31 - Data collection ID (carried with completions) | | |
| 0x10074 | 32 | One over energy in keV (in fixed-point:12 int. + 24 frac. bit format) | R/W | |
| 0x10078 | 32 | Number of frames to be generated by internal packet generator | R/W | |
| 0x1007C | 32 | Number of storage cells | R/W | |
| | | | | |
| 0x20000 - 0x2FFFF | | CMAC 100G | | See Xilinx PG203 for register map |
| 0x30000 - 0x3FFFF | | AXI Mailbox for Work Request / Work Completion | | See Xilinx PG114 for register map |
| 0x40000 - 0x4FFFF | | QuadSPI flash | | See Xilinx PG153 for register map |
| 0x60000 - 0x60FFF | 64 | Input calibration memory addresses block RAM | | |
| 0x70000 - 0x7FFFF | | AXI Firewall | | See Xilinx PG293 for register map |
| 0x80000 - 0x8FFFF | | Interrupt controller | | See Xilinx PG099 for register map |
| 0x70000 - 0x7FFFF | | PCIe DMA control | | See Xilinx PG195 for register map |
| 0xC0000 - 0xFFFFF | | Xilinx Card Management Solution Subsystem management subsystem | | See Xilinx PG348 for register map |
### AXI Mailbox
@@ -105,16 +106,19 @@ Work request has the following structure:
Work completion has the following structure:
| Bit start | Bit end | Meaning |
|-----------|---------|--------------------------------------------------------------------------------------------------------------|
| 0 | 31 | Work request ID (handle) |
| 32 | 39 | Module number |
| 40 | 40 | All packets for the module arrived OK |
| 41 | 41 | Trigger signal high |
| 42 | 62 | Reserved |
| 63 | 63 | Parity bit - bits 0-127 are even parity |
| 64 | 127 | Frame number |
| 128 | 159 | JF debug |
| 160 | 191 | JF Timestamp (low 32-bit) |
| 192 | 255 | Bunch ID |
| 256 | 383 | Optional packet mask (1 bit per packet: 0 packet missing, 1 packet arrived); transmitted only if bit 40 is 0 |
| Bit start | Bit end | Meaning |
|-----------|---------|--------------------------------------------------------------------|
| 0 | 31 | Work request ID (handle) |
| 32 | 39 | Module number |
| 40 | 40 | All packets for the module arrived OK |
| 41 | 41 | Trigger signal high |
| 42 | 62 | Reserved |
| 63 | 63 | Parity bit - bits 0-127 are even parity |
| 64 | 127 | Frame number |
| 128 | 191 | JF Timestamp |
| 192 | 255 | Bunch ID |
| 256 | 287 | Exptime |
| 288 | 319 | JF debug |
| 320 | 351 | Reserved |
| 352 | 383 | Data collection ID (16-bit) |
| 384 | 511 | Packet mask (1 bit per packet: 0 packet missing, 1 packet arrived) |