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xbflash.qspi: Add tool from Xilinx to flash cards (it is a nightmare to...

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2024-10-15 09:27:22 +02:00
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DEPLOYMENT.md
+34 -38
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@@ -2,8 +2,8 @@
To deploy Jungfraujoch, one needs to follow four steps:
1. Flash the U55C FPGA card with a proper image and install Linux kernel driver
2. Install main Jungfraujoch code and frontend web interface
1. Install main Jungfraujoch code and frontend web interface
2. Flash the U55C FPGA card with a proper image and install Linux kernel driver
3. Install Jungfraujoch writer
4. Install Python OpenAPI client
@@ -11,21 +11,38 @@ Installation procedure depend a lot on the operating system. For RedHat Enterpri
installation can be done with prebuilt RPMs and is relatively straightforward. For other systems one needs to build
software from source. Both ways will be presented.
## Install main Jungfraujoch code and frontend web interface
On RHEL 8 systems there is a `jfjoch-<version>-1.el8.x86_64.rpm` that needs to be installed and contains all the necessary software and web interface.
On other OSes one needs to compile Jungfraujoch from source (from the repo directory):
```
$ mkdir build
$ cd build
$ cmake .. -DCMAKE_INSTALL_PREFIX=<directory to install>
$ make
$ sudo make install
```
For manual installation, we recommend to use non-standard directory (like `/opt/jfjoch`), to facilitate upgrades and removal.
Frontend web user interface has to be built separately with:
```
$ cd build
$ make frontend
```
Frontend files (.html and .js) will be placed in `frontend/dist` (outside of `build/` directory!) and has to be copied to a general location, e.g. `/usr/local/jfjoch/frontend` or `/opt/jfjoch/frotend`.
## Flash the U55C FPGA card with a proper image and install Linux kernel driver.
### Firmware flashing
1. Install the `xbflash2` tool from Xilinx, which allows to flash the firmware through PCIe connector.
It can be downloaded as RPM/DEB file from [Alveo product page](https://www.xilinx.com/products/boards-and-kits/alveo/u55c.html#xbflash2). For RHEL9 this needs to built from source - [Xilinx/XRT github repository](https://github.com/Xilinx/XRT).
2. Check that the card is detected by OS with "lspci |grep Xilinx" and check the PCIe slot number (`11:00.0` in this case):
1. Check that the card is detected by OS with "lspci |grep Xilinx" and check the PCIe bus/device/function (BDF) number, `11:00.0` in this case:
```
$ lspci |grep Xilinx
23:00.0 Processing accelerators: Xilinx Corporation Device 3450 (rev 58)
23:00.0 Processing accelerators: Xilinx Corporation Device 3450 (rev 2)
```
Note the device number `3450` that identifies Jungfraujoch device (Jungfraujoch pass is 3450 m above sea level) and `rev 58` identifying release of the firmware.
3. Check the speed of the card, that it is detected as PCIe Gen4x8 device (needs to be done as root, otherwise configuration details are not given):
Note the device number `3450` that identifies Jungfraujoch device (Jungfraujoch pass is 3450 m above sea level) and `rev 2` identifying release of the firmware.
2. Check the speed of the card, that it is detected as PCIe Gen4x8 device (needs to be done as root, otherwise configuration details are not given):
```
$ sudo lspci -vv -s <PCIe slot number>
23:00.0 Processing accelerators: Xilinx Corporation Device 3450
@@ -34,20 +51,20 @@ LnkSta: Speed 16GT/s (ok), Width x8 (ok)
(...)
```
4. Download the MCS image from release files or build it using Vivado (WARNING! building time can be about 8 hours and doesn't allways reach correct timing).
5. Flash the card with xbflash2. For fresh card use:
3. Download the MCS image from release files or build it using Vivado (WARNING! building time can be about 8 hours and doesn't allways reach correct timing).
4. Flash the card with `xbflash.qspi` tool (part of Jungfraujoch). For fresh card use:
```
sudo xbflash2 program --spi --image <path to MCS file> --bar-offset 0x1f06000 -d <PCIe slot from above>
sudo xbflash.qspi --primary <path to MCS file> --card <PCIe slot from above> --bar-offset 0x1f06000
```
For card that was already flashed with Jungfraujoch images:
```
sudo xbflash2 program --spi --image <path to MCS file> -d <PCIe slot from above>
sudo xbflash.qspi --primary <path to MCS file> --card <PCIe slot from above>
```
It is necessary to confirm the operation by pressing `Y` key.
It is necessary to confirm the operation by pressing `Y` key or one can add `--force` option to avoid confirmation.
It is safe to run multiple flashing processes in parallel for different cards, for example in separate screen sessions.
6. Cold reboot:
5. Cold reboot:
```
sudo ipmitool chassis power cycle
```
@@ -82,27 +99,6 @@ $ sudo dracut -f
Configure switch according to [FPGA network guide](fpga/NETWORK.md) - specifically set manual speed and turn off auto-negotiation
for the port used to connect U55C card and connect card to switch.
## Install main Jungfraujoch code and frontend web interface
On RHEL 8 systems there is a `jfjoch-<version>-1.el8.x86_64.rpm` that needs to be installed and contains all the necessary software and web interface.
On other OSes one needs to compile Jungfraujoch from source (from the repo directory):
```
$ mkdir build
$ cd build
$ cmake .. -DCMAKE_INSTALL_PREFIX=<directory to install>
$ make
$ sudo make install
```
For manual installation, we recommend to use non-standard directory (like `/opt/jfjoch`), to facilitate upgrades and removal.
Frontend web user interface has to be built separately with:
```
$ cd build
$ make frontend
```
Frontend files (.html and .js) will be placed in `frontend/dist` (outside of `build/` directory!) and has to be copied to a general location, e.g. `/usr/local/jfjoch/frontend` or `/opt/jfjoch/frotend`.
### Running Jungfraujoch software
Main Jungfraujoch service is called `jfjoch_broker`. It is responsible for handling data from FPGAs, doing processing, analysis, compression and sending images on ZeroMQ output.
It is recommended to run the service as `systemd` service.
fpga/host_library/CMakeLists.txt
+3 -2
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@@ -8,11 +8,12 @@ INSTALL(TARGETS jfjoch_pcie_status RUNTIME COMPONENT jfjoch)
ADD_EXECUTABLE(jfjoch_pcie_net_cfg jfjoch_pcie_net_cfg.cpp)
TARGET_LINK_LIBRARIES(jfjoch_pcie_net_cfg JFJochDevice )
INSTALL(TARGETS jfjoch_pcie_net_cfg RUNTIME)
INSTALL(TARGETS jfjoch_pcie_net_cfg RUNTIME COMPONENT jfjoch )
ADD_EXECUTABLE(jfjoch_pcie_clear_net_counters jfjoch_pcie_clear_net_counters.cpp)
TARGET_LINK_LIBRARIES(jfjoch_pcie_clear_net_counters JFJochDevice )
INSTALL(TARGETS jfjoch_pcie_clear_net_counters RUNTIME)
INSTALL(TARGETS jfjoch_pcie_clear_net_counters RUNTIME COMPONENT jfjoch )
# Clock cfg test is not too important to be installed as part of Jungfraujoch
ADD_EXECUTABLE(jfjoch_pcie_clock_cfg_test jfjoch_pcie_clock_cfg_test.cpp)
TARGET_LINK_LIBRARIES(jfjoch_pcie_clock_cfg_test JFJochDevice )
gitlab_upload_release.sh
+9 -9
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@@ -5,7 +5,7 @@
#
export PACKAGE_VERSION_SEM=`head -n1 VERSION`
export FPGA_VERSION="1.0.0-rc.14"
export FPGA_VERSION="1.0.0-rc.16"
export PACKAGE_VERSION=${PACKAGE_VERSION_SEM//-/_}
export PACKAGE_VERSION_PYTHON=${PACKAGE_VERSION_SEM//-rc./rc}
export PACKAGE_VERSION_PYTHON=${PACKAGE_VERSION_PYTHON//-alpha./a}
@@ -23,12 +23,12 @@ curl --header "JOB-TOKEN: $CI_JOB_TOKEN" --upload-file jfjoch_frontend.tar.gz "$
curl --header "JOB-TOKEN: $CI_JOB_TOKEN" --upload-file jfjoch-client-${PACKAGE_VERSION_PYTHON}.tar.gz "${PACKAGE_REGISTRY_URL}/jfjoch-client-${PACKAGE_VERSION_PYTHON}.tar.gz"
curl --header "JOB-TOKEN: $CI_JOB_TOKEN" --upload-file jfjoch_client-${PACKAGE_VERSION_PYTHON}-py3-none-any.whl "${PACKAGE_REGISTRY_URL}/jfjoch_client-${PACKAGE_VERSION_PYTHON}-py3-none-any.whl"
release-cli create --name "Release $PACKAGE_VERSION_SEM" --tag-name $PACKAGE_VERSION_SEM
--assets-link "{\"name\":\"jfjoch_frontend.tar.gz\",\"url\":\"${PACKAGE_REGISTRY_URL}/jfjoch_frontend.tar.gz\"}"
--assets-link "{\"name\":\"jfjoch_fpga_pcie_8x10g.mcs\",\"url\":\"${FPGA_REGISTRY_URL}/jfjoch_fpga_pcie_8x10g.mcs\"}"
--assets-link "{\"name\":\"jfjoch_fpga_pcie_100g.mcs\",\"url\":\"${FPGA_REGISTRY_URL}/jfjoch_fpga_pcie_100g.mcs\"}"
--assets-link "{\"name\":\"jfjoch-${PACKAGE_VERSION}-1.el8.x86_64.rpm\",\"url\":\"${PACKAGE_REGISTRY_URL}/jfjoch-${PACKAGE_VERSION}-1.el8.x86_64.rpm\",\"link_type\":\"package\"}"
--assets-link "{\"name\":\"jfjoch-writer-${PACKAGE_VERSION}-1.el8.x86_64.rpm\",\"url\":\"${PACKAGE_REGISTRY_URL}/jfjoch-writer-${PACKAGE_VERSION}-1.el8.x86_64.rpm\",\"link_type\":\"package\"}"
--assets-link "{\"name\":\"jfjoch-driver-dkms-${PACKAGE_VERSION}-1.el8.noarch.rpm\",\"url\":\"${PACKAGE_REGISTRY_URL}/jfjoch-driver-dkms-${PACKAGE_VERSION}-1.el8.noarch.rpm\",\"link_type\":\"package\"}"
--assets-link "{\"name\":\"jfjoch_client-${PACKAGE_VERSION_PYTHON}-py3-none-any.whl\",\"url\":\"${PACKAGE_REGISTRY_URL}/jfjoch_client-${PACKAGE_VERSION_PYTHON}-py3-none-any.whl\",\"link_type\":\"package\"}"
release-cli create --name "Release $PACKAGE_VERSION_SEM" --tag-name $PACKAGE_VERSION_SEM \
--assets-link "{\"name\":\"jfjoch_frontend.tar.gz\",\"url\":\"${PACKAGE_REGISTRY_URL}/jfjoch_frontend.tar.gz\"}" \
--assets-link "{\"name\":\"jfjoch_fpga_pcie_8x10g.mcs\",\"url\":\"${FPGA_REGISTRY_URL}/jfjoch_fpga_pcie_8x10g.mcs\"}" \
--assets-link "{\"name\":\"jfjoch_fpga_pcie_100g.mcs\",\"url\":\"${FPGA_REGISTRY_URL}/jfjoch_fpga_pcie_100g.mcs\"}" \
--assets-link "{\"name\":\"jfjoch-${PACKAGE_VERSION}-1.el8.x86_64.rpm\",\"url\":\"${PACKAGE_REGISTRY_URL}/jfjoch-${PACKAGE_VERSION}-1.el8.x86_64.rpm\",\"link_type\":\"package\"}" \
--assets-link "{\"name\":\"jfjoch-writer-${PACKAGE_VERSION}-1.el8.x86_64.rpm\",\"url\":\"${PACKAGE_REGISTRY_URL}/jfjoch-writer-${PACKAGE_VERSION}-1.el8.x86_64.rpm\",\"link_type\":\"package\"}" \
--assets-link "{\"name\":\"jfjoch-driver-dkms-${PACKAGE_VERSION}-1.el8.noarch.rpm\",\"url\":\"${PACKAGE_REGISTRY_URL}/jfjoch-driver-dkms-${PACKAGE_VERSION}-1.el8.noarch.rpm\",\"link_type\":\"package\"}" \
--assets-link "{\"name\":\"jfjoch_client-${PACKAGE_VERSION_PYTHON}-py3-none-any.whl\",\"url\":\"${PACKAGE_REGISTRY_URL}/jfjoch_client-${PACKAGE_VERSION_PYTHON}-py3-none-any.whl\",\"link_type\":\"package\"}" \
--assets-link "{\"name\":\"jfjoch-client-${PACKAGE_VERSION_PYTHON}.tar.gz\",\"url\":\"${PACKAGE_REGISTRY_URL}/jfjoch-client-${PACKAGE_VERSION_PYTHON}.tar.gz\",\"link_type\":\"package\"}"
tools/CMakeLists.txt
+2
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@@ -24,3 +24,5 @@ ADD_EXECUTABLE(AzimIntDataset AzimIntDataset.cpp)
TARGET_LINK_LIBRARIES(AzimIntDataset JFJochImageAnalysis JFJochWriter JFJochCommon)
INSTALL(TARGETS jfjoch_udp_simulator HDF5DatasetWriteTest jfjoch_writer_test AzimIntDataset RUNTIME)
ADD_SUBDIRECTORY(xbflash.qspi)
tools/xbflash.qspi/CMakeLists.txt
+16
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@@ -0,0 +1,16 @@
# SPDX-License-Identifier: Apache-2.0
# Copyright (C) 2019-2021 Xilinx, Inc. All rights reserved.
#
add_executable(xbflash.qspi
firmware_image.cpp
firmware_image.h
main.cpp
pcidev.cpp
pcidev.h
xqspips.cpp
xqspips.h
xspi.cpp
xspi.h)
INSTALL(TARGETS xbflash.qspi RUNTIME COMPONENT jfjoch )
tools/xbflash.qspi/LICENSE
+517
View File
@@ -0,0 +1,517 @@
All userspace code authored by Xilinx or Advanced Micro Devices is
released under the following license:
Copyright (C) 2016-2022 Xilinx, Inc
Copyright (C) 2022-2023 Advanced Micro Devices, Inc
Licensed under the Apache License, Version 2.0 (the "License"). You may
not use this file except in compliance with the License. A copy of the
License is located at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
License for the specific language governing permissions and limitations
under the License.
All Linux kernel driver code included in "xocl" or "xclmgmt" authored by
Xilinx is released under the terms of GNU General Public License version 2:
Copyright (C) 2016-2022 Xilinx, Inc. All rights reserved.
Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All rights reserved.
This software is licensed under the terms of the GNU General Public
License version 2, as published by the Free Software Foundation, and
may be copied, distributed, and modified under those terms.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
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GNU General Public License for more details.
All Linux kernel driver code included in "zocl" authored by Xilinx is
released under the terms of either Apache License, Version 2.0,
or alternatively under the terms of the GNU General Public License
version 2:
Copyright (C) 2016-2020 Xilinx, Inc. All rights reserved.
Copyright (C) 2022-2023 Advanced Micro Devices, Inc. All rights reserved.
This software is licensed under the terms of the GNU General Public
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This program is distributed in the hope that it will be useful,
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You may use the Linux kernel driver code according to either of these
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a warranty) and that users may redistribute the program under
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the Program is not required to print an announcement.)
These requirements apply to the modified work as a whole. If
identifiable sections of that work are not derived from the Program,
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Thus, it is not the intent of this section to claim rights or contest
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In addition, mere aggregation of another work not based on the Program
with the Program (or with a work based on the Program) on a volume of
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the scope of this License.
3. You may copy and distribute the Program (or a work based on it,
under Section 2) in object code or executable form under the terms of
Sections 1 and 2 above provided that you also do one of the following:
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4. You may not copy, modify, sublicense, or distribute the Program
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5. You are not required to accept this License, since you have not
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NO WARRANTY
11. BECAUSE THE PROGRAM IS LICENSED FREE OF CHARGE, THERE IS NO WARRANTY
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END OF TERMS AND CONDITIONS
tools/xbflash.qspi/README.md
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# xbflash.qspi
This program allows to flash firmware of Xilinx/AMD FPGA cards via PCIe edge and QSPI core.
This tool is taken from the Xilinx/AMD [XRT repository](https://githb.com/Xilinx/XRT) and extracted for convenience, since the original repository has
an extreme number of dependencies.
Note: Xilinx has two tools `xbflash.qspi` and `xbflash2`.
The latter is only repackaging of the original code with extra Boost libraries for nice options parsing.
Thus, we decided not to only take the original program, to not increase number of dependencies of the code.
## Usage
`xbflash.qspi` has to be run as root.
```
xbflash.qspi --primary <name of image> --card <PCIe id of the card>
```
tools/xbflash.qspi/firmware_image.cpp
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/**
* Copyright (C) 2020-2021 Xilinx, Inc
*
* Licensed under the Apache License, Version 2.0 (the "License"). You may
* not use this file except in compliance with the License. A copy of the
* License is located at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*/
#include <fstream>
#include "firmware_image.h"
firmwareImage::firmwareImage(const char *file) :
mBuf(nullptr)
{
std::ifstream in(file, std::ios::binary | std::ios::ate);
if (!in.is_open())
{
this->setstate(failbit);
std::cout << "Can't open " << file << std::endl;
return;
}
auto bufsize = in.tellg();
in.seekg(0);
// For non-dsabin file, the entire file is the image.
mBuf = new char[bufsize];
in.seekg(0);
in.read(mBuf, bufsize);
this->rdbuf()->pubsetbuf(mBuf, bufsize);
}
firmwareImage::~firmwareImage()
{
delete[] mBuf;
}
tools/xbflash.qspi/firmware_image.h
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/**
* Copyright (C) 2018 Xilinx, Inc
*
* Licensed under the Apache License, Version 2.0 (the "License"). You may
* not use this file except in compliance with the License. A copy of the
* License is located at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*/
/*
* Contains definitions for all firmware (DSA/BMC) related classes
*/
#ifndef _FIRMWARE_IMAGE_H_
#define _FIRMWARE_IMAGE_H_
#include <iostream>
#include <sstream>
class firmwareImage : public std::istringstream
{
public:
firmwareImage(const char *file);
~firmwareImage();
private:
char *mBuf;
};
#endif
tools/xbflash.qspi/main.cpp
+565
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/**
* Copyright (C) 2020 Xilinx, Inc
*
* Licensed under the Apache License, Version 2.0 (the "License"). You may
* not use this file except in compliance with the License. A copy of the
* License is located at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*/
//
// This utility is implemented by porting flash code from xbmgmt. Since that
// it's used only by non-XRT users, we do not expect to maintain and enhance
// this code a lot in the future. Hence, no cleanup effort is ever attempted
// while porting the code from xbmgmt at this point.
// If it works, don't change it.
//
#include <iostream>
#include <memory>
#include <cstdlib>
#include <cstring>
#include <sys/types.h>
#include <getopt.h>
#include <libgen.h>
#include <unistd.h>
#include "pcidev.h"
#include "xspi.h"
#include "xqspips.h"
#include "firmware_image.h"
const option flash_opts[] = {
// Key option to identify flash operation, must be 0
{ "primary", required_argument, nullptr, '0' },
{ "force", no_argument, nullptr, '1' },
{ "card", required_argument, nullptr, '2' },
{ "secondary", required_argument, nullptr, '3' },
{ "bar", required_argument, nullptr, '4' },
{ "bar-offset", required_argument, nullptr, '5' },
{ nullptr, 0, nullptr, 0 },
};
const option reset_opts[] = {
// Key option to identify reset operation, must be 0
{ "factory-reset", no_argument, nullptr, '0' },
{ "force", no_argument, nullptr, '1' },
{ "card", required_argument, nullptr, '2' },
{ "dual-flash", no_argument, nullptr, '3' },
{ "bar", required_argument, nullptr, '4' },
{ "bar-offset", required_argument, nullptr, '5' },
{ nullptr, 0, nullptr, 0 },
};
const option qspips_erase_opts[] = {
// Key option to identify flash operation, must be 0
{ "qspips-erase", no_argument, nullptr, '0' },
{ "card", required_argument, nullptr, '1' },
{ "offset", required_argument, nullptr, '2' },
{ "length", required_argument, nullptr, '3' },
{ "flash-type", required_argument, nullptr, '4' },
{ "bar", required_argument, nullptr, '5' },
{ "bar-offset", required_argument, nullptr, '6' },
{ "force", no_argument, nullptr, '7' },
{ nullptr, 0, nullptr, 0 },
};
const option qspips_flash_opts[] = {
// Key option to identify flash operation, must be 0
{ "qspips-flash", no_argument, nullptr, '0' },
{ "card", required_argument, nullptr, '1' },
{ "input", required_argument, nullptr, '2' },
{ "offset", required_argument, nullptr, '3' },
{ "flash-type", required_argument, nullptr, '4' },
{ "bar", required_argument, nullptr, '5' },
{ "bar-offset", required_argument, nullptr, '6' },
{ "force", no_argument, nullptr, '7' },
{ nullptr, 0, nullptr, 0 },
};
const option qspips_readback_opts[] = {
// Key option to identify flash operation, must be 0
{ "qspips-read", no_argument, nullptr, '0' },
{ "card", required_argument, nullptr, '1' },
{ "output", required_argument, nullptr, '2' },
{ "offset", required_argument, nullptr, '3' },
{ "length", required_argument, nullptr, '4' },
{ "flash-type", required_argument, nullptr, '5' },
{ "bar", required_argument, nullptr, '6' },
{ "bar-offset", required_argument, nullptr, '7' },
{ nullptr, 0, nullptr, 0 },
};
static const char *option_key(const option *opts)
{
while (opts->name != nullptr) {
if (opts->val == '0')
return opts->name;
opts++;
}
return nullptr;
}
static bool is_op(const option *opts, int argc, char *argv[])
{
const char *key = option_key(opts);
std::string optkey = "--";
if (key == nullptr)
return false;
optkey += key;
for (int i = 0; i < argc; i++) {
if (optkey.compare(argv[i]) == 0)
return true;
}
return false;
}
static void sudoOrDie()
{
const char* SudoMessage = "ERROR: root privileges required.";
if ((getuid() == 0) || (geteuid() == 0))
return;
std::cout << SudoMessage << std::endl;
exit(-EPERM);
}
static bool canProceed()
{
std::string input;
bool answered = false;
bool proceed = false;
while (!answered) {
std::cout << "Are you sure you wish to proceed? [y/n]: ";
std::cin >> input;
answered = (input.compare("y") == 0 || input.compare("n") == 0);
}
proceed = (input.compare("y") == 0);
if (!proceed)
std::cout << "Action canceled." << std::endl;
return proceed;
}
static void printHelp(const char *fname)
{
auto tmp = std::unique_ptr<char, decltype(std::free)*>{strdup(fname), std::free};
std::cout << "Usage: " << std::endl;
std::cout << basename(tmp.get()) << " [options]" << std::endl;
std::cout << "\nOptions:" << std::endl;
std::cout << "\n\"SPI flash\"\n";
std::cout << " --primary, <MCS-path>, must be 1st option\n";
std::cout << " [--secondary <MCS-path>], default is empty\n";
std::cout << " --card <BDF>\n";
std::cout << " [--force, yes for prompt]\n";
std::cout << " [--bar <BAR-index-for-QSPI>], default is 0\n";
std::cout << " [--bar-offset <BAR-offset-for-QSPI>], default is 0x40000\n";
std::cout << "\n\"SPI factory-reset\"\n";
std::cout << " --factory-reset, must be 1st option\n";
std::cout << " [--dual-flash]\n";
std::cout << " --card <BDF>\n";
std::cout << " [--force, yes for prompt]\n";
std::cout << " [--bar <BAR-index-for-QSPI>], default is 0\n";
std::cout << " [--bar-offset <BAR-offset-for-QSPI>], default is 0x40000\n";
std::cout << "\n\"QSPIPS erase\"\n";
std::cout << " --qspips-erase, must be 1st option\n";
std::cout << " --card <BDF>\n";
std::cout << " [--offset <offset-on-flash-to-start-with>], default is 0\n";
std::cout << " [--length <length-to-read>], default is 96MB\n";
std::cout << " [--flash-type <qspips-flash-type>], default is qspi_ps_x2_single\n";
std::cout << " [--bar <BAR-index-for-QSPIPS>], default is 0\n";
std::cout << " [--bar-offset <BAR-offset-for-QSPIPS>], default is 0x40000\n";
std::cout << " [--force, yes for prompt]\n";
std::cout << "\n\"QSPIPS flash\"\n";
std::cout << " --qspips-flash, must be 1st option\n";
std::cout << " --input <path-to-qspips-BOOT-BIN-file>\n";
std::cout << " --card <BDF>\n";
std::cout << " [--offset <offset-on-flash-to-start-with>], default is 0\n";
std::cout << " [--flash-type <qspips-flash-type>], default is qspi_ps_x2_single\n";
std::cout << " [--bar <BAR-index-for-QSPIPS>], default is 0\n";
std::cout << " [--bar-offset <BAR-offset-for-QSPIPS>], default is 0x40000\n";
std::cout << " [--force, yes for prompt]\n";
std::cout << "\n\"QSPIPS read back\"\n";
std::cout << " --qspips-read, must be 1st option\n";
std::cout << " --output <output-file-to-save-read-contents>\n";
std::cout << " --card <BDF>\n";
std::cout << " [--offset <offset-on-flash-to-start-with>], default is 0\n";
std::cout << " [--length <length-to-read>], default is 128MB\n";
std::cout << " [--flash-type <qspips-flash-type>], default is qspi_ps_x2_single\n";
std::cout << " [--bar <BAR-index-for-QSPIPS>], default is 0\n";
std::cout << " [--bar-offset <BAR-offset-for-QSPIPS>], default is 0x40000\n";
}
int reset(int argc, char *argv[])
{
bool force = false;
std::string bdf;
const char *fname = argv[0];
int bar = 0;
size_t baroff = INVALID_OFFSET;
bool dualflash = false;
sudoOrDie();
while (true) {
const auto opt = getopt_long(argc, argv, "", reset_opts, nullptr);
if (opt == -1)
break;
switch (opt) {
case '2':
bdf = std::string(optarg);
break;
case '1':
force = true;
break;
case '0':
break;
case '3':
dualflash = true;
break;
case '4':
bar = std::stoi(optarg, nullptr, 0);
break;
case '5':
baroff = std::stoi(optarg, nullptr, 0);
break;
default:
printHelp(fname);
return -EINVAL;
}
}
if (bdf.empty()) {
printHelp(fname);
return -EINVAL;
}
std::cout
<< "About to revert to golden image for card " << bdf << std::endl;
if (!force && !canProceed())
return -ECANCELED;
pcidev::pci_device dev(bdf, bar, baroff);
XSPI_Flasher xspi(&dev, dualflash);
return xspi.revertToMFG();
}
int flash(int argc, char *argv[])
{
int ret = 0;
bool force = false;
std::string primary_file;
std::string secondary_file;
std::string bdf;
const char *fname = argv[0];
int bar = 0;
size_t baroff = INVALID_OFFSET;
sudoOrDie();
while (true) {
const auto opt = getopt_long(argc, argv, "", flash_opts, nullptr);
if (opt == -1)
break;
switch (opt) {
case '2':
bdf = std::string(optarg);
break;
case '1':
force = true;
break;
case '0':
primary_file = std::string(optarg);
break;
case '3':
secondary_file = std::string(optarg);
break;
case '4':
bar = std::stoi(optarg);
break;
case '5':
baroff = std::stoi(optarg, nullptr, 0);
break;
default:
printHelp(fname);
return -EINVAL;
}
}
if (bdf.empty() || primary_file.empty()) {
printHelp(fname);
return -EINVAL;
}
std::cout
<< "About to flash below MCS bitstream onto card "
<< bdf << ":" << std::endl;
std::cout << primary_file << std::endl;
if (!secondary_file.empty())
std::cout << secondary_file << std::endl;
if (!force && !canProceed())
return -ECANCELED;
pcidev::pci_device dev(bdf, bar, baroff);
XSPI_Flasher xspi(&dev, !secondary_file.empty());
if (secondary_file.empty()) {
firmwareImage pri(primary_file.c_str());
if (pri.fail())
return -EINVAL;
ret = xspi.xclUpgradeFirmware1(pri);
} else {
firmwareImage pri(primary_file.c_str());
firmwareImage sec(secondary_file.c_str());
if (pri.fail() || sec.fail())
return -EINVAL;
ret = xspi.xclUpgradeFirmware2(pri, sec);
}
return ret;
}
int qspips_erase(int argc, char *argv[])
{
std::string bdf;
const char *fname = argv[0];
int bar = 0;
size_t baroff = INVALID_OFFSET;
std::string flash_type;
size_t offset = 0, len = GOLDEN_BASE;
bool force = false;
sudoOrDie();
while (true) {
const auto opt = getopt_long(argc, argv, "", qspips_erase_opts, nullptr);
if (opt == -1)
break;
switch (opt) {
case '0':
break;
case '1':
bdf = std::string(optarg);
break;
case '2':
offset = std::stoi(optarg, nullptr, 0);
break;
case '3':
len = std::stoi(optarg, nullptr, 0);
break;
case '4':
flash_type = std::string(optarg);
break;
case '5':
bar = std::stoi(optarg);
break;
case '6':
baroff = std::stoi(optarg, nullptr, 0);
break;
case '7':
force = true;
break;
default:
printHelp(fname);
return -EINVAL;
}
}
if (bdf.empty()) {
printHelp(fname);
return -EINVAL;
}
std::cout << "About to erase flash"
<< " [0x" << std::hex << offset << ",0x" << offset+len
<< "] on card " << bdf << std::endl;
if (offset + len > GOLDEN_BASE)
std::cout << "\nThis might erase golden image if there is !!\n" << std::endl;
if (!force && !canProceed())
return -ECANCELED;
pcidev::pci_device dev(bdf, bar, baroff, flash_type);
XQSPIPS_Flasher qspips(&dev);
return qspips.xclErase(offset, len);
}
int qspips_flash(int argc, char *argv[])
{
std::string bdf;
const char *fname = argv[0];
int bar = 0;
size_t baroff = INVALID_OFFSET;
size_t offset = 0;
std::string flash_type;
std::string bin_file;
bool force = false;
sudoOrDie();
while (true) {
const auto opt = getopt_long(argc, argv, "", qspips_flash_opts, nullptr);
if (opt == -1)
break;
switch (opt) {
case '0':
break;
case '1':
bdf = std::string(optarg);
break;
case '2':
bin_file = std::string(optarg);
break;
case '3':
offset = std::stoi(optarg, nullptr, 0);
break;
case '4':
flash_type = std::string(optarg);
break;
case '5':
bar = std::stoi(optarg);
break;
case '6':
baroff = std::stoi(optarg, nullptr, 0);
break;
case '7':
force = true;
break;
default:
printHelp(fname);
return -EINVAL;
}
}
if (bdf.empty() || bin_file.empty()) {
printHelp(fname);
return -EINVAL;
}
firmwareImage bin(bin_file.c_str());
if (bin.fail())
return -EINVAL;
std::cout
<< "About to program flash on card " << bdf << " at offset 0x" << std::hex << offset << std::dec << std::endl;
if (!force && !canProceed())
return -ECANCELED;
pcidev::pci_device dev(bdf, bar, baroff, flash_type);
XQSPIPS_Flasher qspips(&dev);
return qspips.xclUpgradeFirmware(bin, offset);
}
int qspips_readback(int argc, char *argv[])
{
std::string bdf;
const char *fname = argv[0];
int bar = 0;
size_t baroff = INVALID_OFFSET;
size_t offset = 0, len = FLASH_SIZE;
std::string flash_type;
std::string output;
sudoOrDie();
while (true) {
const auto opt = getopt_long(argc, argv, "", qspips_readback_opts, nullptr);
if (opt == -1)
break;
switch (opt) {
case '0':
break;
case '1':
bdf = std::string(optarg);
break;
case '2':
output = std::string(optarg);
break;
case '3':
offset = std::stoi(optarg, nullptr, 0);
break;
case '4':
len = std::stoi(optarg, nullptr, 0);
break;
case '5':
flash_type = std::string(optarg);
break;
case '6':
bar = std::stoi(optarg);
break;
case '7':
baroff = std::stoi(optarg, nullptr, 0);
break;
default:
printHelp(fname);
return -EINVAL;
}
}
if (bdf.empty() || output.empty()) {
printHelp(fname);
return -EINVAL;
}
std::cout << "Read out flash"
<< " [0x" << std::hex << offset << ",0x" << offset+len
<< "] on card " << bdf << " to " << output << std::dec << std::endl;
pcidev::pci_device dev(bdf, bar, baroff, flash_type);
XQSPIPS_Flasher qspips(&dev);
return qspips.xclReadBack(output, offset, len);
}
int main(int argc, char *argv[])
{
try {
if (is_op(reset_opts, argc, argv))
return reset(argc, argv);
if (is_op(flash_opts, argc, argv))
return flash(argc, argv);
if (is_op(qspips_erase_opts, argc, argv))
return qspips_erase(argc, argv);
if (is_op(qspips_flash_opts, argc, argv))
return qspips_flash(argc, argv);
if (is_op(qspips_readback_opts, argc, argv))
return qspips_readback(argc, argv);
} catch (const std::exception& ex) {
std::cout << "Failed to flash: " << ex.what() << std::endl;
return -EINVAL;
}
printHelp(argv[0]);
return -EINVAL;
}
tools/xbflash.qspi/pcidev.cpp
+228
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/**
* Copyright (C) 2020 Xilinx, Inc
*
* Licensed under the Apache License, Version 2.0 (the "License"). You may
* not use this file except in compliance with the License. A copy of the
* License is located at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*/
#include <cassert>
#include <iostream>
#include <cstring>
#include <unistd.h>
#include <mutex>
#include <sys/stat.h>
#include <sys/file.h>
#include <linux/pci.h>
#include "pcidev.h"
namespace pcidev {
/*
* wordcopy()
*
* Copy bytes word (32bit) by word.
* Neither memcpy, nor std::copy work as they become byte copying
* on some platforms.
*/
inline void*
wordcopy(void *dst, const void* src, size_t bytes)
{
// assert dest is 4 byte aligned
assert((reinterpret_cast<intptr_t>(dst) % 4) == 0);
using word = uint32_t;
volatile auto d = reinterpret_cast<word*>(dst);
auto s = reinterpret_cast<const word*>(src);
auto w = bytes/sizeof(word);
for (size_t i=0; i<w; ++i)
d[i] = s[i];
return dst;
}
int
pci_device::
open(const std::string& subdev, int flag)
{
int fd = -1;
// Open legacy subdevice node
std::string file("/dev/xfpga/");
file += subdev;
file += ".m";
file += std::to_string((uint32_t)(domain<<16) + (bus<<8) + (dev<<3) + func);
file += "." + std::to_string(0);
fd = ::open(file.c_str(), flag);
if (fd >= 0) {
std::cout << "Successfully opened " << file << std::endl;
return fd;
}
// Open xoclv2 subdevice node
char bdf[20];
std::snprintf(bdf, sizeof(bdf), "%04x:%02x:%02x.%x", domain, bus, dev, func);
file = "/dev/xfpga/";
file += subdev;
file += ".";
file += bdf;
fd = ::open(file.c_str(), flag);
if (fd >= 0) {
std::cout << "Successfully opened " << file << std::endl;
return fd;
}
return fd;
}
pci_device::
pci_device(const std::string& sysfs, int ubar, size_t flash_off, std::string flash_type)
: user_bar_index(ubar), flash_offset(flash_off), flash_type_str(flash_type)
{
uint32_t pcmd = 0;
char sysfsname[20] = {0};
uint16_t dom = 0, b, d, f;
if (sscanf(sysfs.c_str(), "%hx:%hx.%hx", &b, &d, &f) < 3 &&
sscanf(sysfs.c_str(), "%hx:%hx:%hx.%hx", &dom, &b, &d, &f) < 4)
throw std::runtime_error("Couldn't parse entry name " + sysfs);
domain = dom;
bus = b;
dev = d;
func = f;
user_bar_size = 0;
std::snprintf(sysfsname, sizeof(sysfsname), "%04x:%02x:%02x.%x",
domain, bus, dev, func);
std::string conffile("/sys/bus/pci/devices/");
conffile += sysfsname;
conffile += "/config";
int conf_handle = ::open(conffile.c_str(), O_RDWR | O_SYNC);
if (conf_handle < 0) {
throw std::runtime_error("Failed to open " + conffile);
}
if(lseek(conf_handle, 4, SEEK_SET) != 4)
throw std::runtime_error("Failed to set file pointer for " + conffile);
if(::read(conf_handle, &pcmd, 4) < 0)
throw std::runtime_error("Failed to read " + conffile);
pcmd = pcmd | PCI_COMMAND_MEMORY;
if(lseek(conf_handle, 4, SEEK_SET) != 4)
throw std::runtime_error("Failed to set file pointer for " + conffile);
if(::write(conf_handle, &pcmd, 4) < 0)
throw std::runtime_error("Failed to write " + conffile);
close(conf_handle);
}
pci_device::
~pci_device()
{
if (user_bar_map != MAP_FAILED)
::munmap(user_bar_map, user_bar_size);
}
int
pci_device::
map_usr_bar()
{
std::lock_guard<std::mutex> l(lock);
if (user_bar_map != MAP_FAILED)
return 0;
char sysfsname[20];
std::snprintf(sysfsname, sizeof(sysfsname), "%04x:%02x:%02x.%x",
domain, bus, dev, func);
std::string resfile("/sys/bus/pci/devices/");
resfile += sysfsname;
resfile += "/resource";
resfile += std::to_string(user_bar_index);
int dev_handle = ::open(resfile.c_str(), O_RDWR | O_SYNC);
if (dev_handle < 0) {
int err = errno;
std::cout << "Failed to open " << resfile << " : "
<< strerror(err) << std::endl;
return -err;
}
struct stat sb;
if (fstat(dev_handle, &sb) == -1) { // To obtain file size
int err = errno;
std::cout << "Failed to stat " << resfile << ": "
<< strerror(err) << std::endl;
(void) close(dev_handle);
return -err;
}
user_bar_size = sb.st_size;
user_bar_map = (char *)::mmap(0, user_bar_size, PROT_READ | PROT_WRITE,
MAP_SHARED, dev_handle, 0);
// Mapping should stay valid after handle is closed
// (according to man page)
(void)close(dev_handle);
if (user_bar_map == MAP_FAILED) {
int err = errno;
std::cout << "Failed to map " << resfile << ": "
<< strerror(err) << std::endl;
return -err;
}
return 0;
}
void
pci_device::
close(int dev_handle)
{
if (dev_handle != -1)
(void)::close(dev_handle);
}
int
pci_device::
pcieBarRead(uint64_t offset, void* buf, uint64_t len)
{
if (user_bar_map == MAP_FAILED) {
int ret = map_usr_bar();
if (ret) {
std::cout << "Failed to map in PCIE BAR. Does the card specified exist?" << std::endl;
throw;
}
}
(void) wordcopy(buf, user_bar_map + offset, len);
return 0;
}
int
pci_device::
pcieBarWrite(uint64_t offset, const void* buf, uint64_t len)
{
if (user_bar_map == MAP_FAILED) {
int ret = map_usr_bar();
if (ret)
return ret;
}
(void) wordcopy(user_bar_map + offset, buf, len);
return 0;
}
} // namespace pcidev
tools/xbflash.qspi/pcidev.h
+58
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/**
* Copyright (C) 2020 Xilinx, Inc
*
* Licensed under the Apache License, Version 2.0 (the "License"). You may
* not use this file except in compliance with the License. A copy of the
* License is located at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*/
#ifndef _PCIDEV_H_
#define _PCIDEV_H_
#include <string>
#include <sys/mman.h>
#include <mutex>
#define INVALID_ID ((uint16_t)-1)
namespace pcidev {
// One PCIE function on FPGA board
class pci_device
{
public:
pci_device(const std::string& sysfs, int ubar, size_t flash_off, std::string flash_type = "");
~pci_device();
int pcieBarRead(uint64_t offset, void *buf, uint64_t len);
int pcieBarWrite(uint64_t offset, const void *buf, uint64_t len);
int open(const std::string& subdev, int flag);
void close(int devhdl);
size_t get_flash_offset() { return flash_offset; }
int get_flash_bar_index() { return user_bar_index; }
std::string get_flash_type() { return flash_type_str; };
private:
uint16_t domain = INVALID_ID;
uint16_t bus = INVALID_ID;
uint16_t dev = INVALID_ID;
uint16_t func = INVALID_ID;
int map_usr_bar(void);
std::mutex lock;
char *user_bar_map = reinterpret_cast<char *>(MAP_FAILED);
int user_bar_index;
size_t user_bar_size;
size_t flash_offset;
std::string flash_type_str;
};
} // namespace pcidev
#endif
tools/xbflash.qspi/xqspips.cpp
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tools/xbflash.qspi/xqspips.h
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/**
* Copyright (C) 2016-2018 Xilinx, Inc
* Author(s) : Min Ma
*
* Licensed under the Apache License, Version 2.0 (the "License"). You may
* not use this file except in compliance with the License. A copy of the
* License is located at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*/
#ifndef _XQSPIPS_H_
#define _XQSPIPS_H_
#include <sys/stat.h>
#include <list>
#include <iostream>
#include "pcidev.h"
#define PAGE_SIZE 256
#define PAGE_8K 8192
#define GOLDEN_BASE 0x06000000
#define FLASH_SIZE 0x08000000
#define INVALID_OFFSET ((size_t)-1)
class XQSPIPS_Flasher
{
struct ELARecord
{
unsigned mStartAddress;
unsigned mEndAddress;
unsigned mDataCount;
std::streampos mDataPos;
ELARecord() : mStartAddress(0), mEndAddress(0), mDataCount(0), mDataPos(0) {}
};
typedef std::list<ELARecord> ELARecordList;
ELARecordList mRecordList;
public:
XQSPIPS_Flasher(pcidev::pci_device *dev);
~XQSPIPS_Flasher();
void program(std::istream& binStream, unsigned base = 0);
int verify(std::istream& binStream, unsigned base = 0, bool quiet = false);
int revertToMFG(std::istream& binStream);
int xclUpgradeFirmware(std::istream& binStream, unsigned offset = 0);
int xclErase(unsigned offset = 0, unsigned total_size = GOLDEN_BASE);
int xclReadBack(std::string output, unsigned base = 0, unsigned total_size = FLASH_SIZE);
private:
typedef struct {
uint8_t *bufPtr;
uint32_t byteCount;
uint32_t busWidth;
uint32_t flags;
} xqspips_msg_t;
pcidev::pci_device *mDev;
uint8_t mWriteBuffer[PAGE_8K];
uint8_t mReadBuffer[PAGE_8K];
uint32_t mTxBytes;
uint32_t mRxBytes;
uint64_t flash_base;
/* QSPI configure */
uint32_t mConnectMode; //Single, Stacked and Parallel mode
uint32_t mBusWidth; // x1, x2, x4
void clearReadBuffer(unsigned size);
void clearWriteBuffer(unsigned size);
void clearBuffers(unsigned size);
/* Flash functions */
int xclTestXQSpiPS(int device_index);
bool getFlashID();
bool isFlashReady();
bool readFlashReg(unsigned commandCode, unsigned bytes);
bool writeFlashReg(unsigned commandCode, unsigned value, unsigned bytes);
bool eraseSector(unsigned addr, uint32_t byteCount, uint8_t eraseCmd = 0xff);
bool eraseBulk();
bool readFlash(unsigned addr, uint32_t byteCount, uint8_t readCmd = 0xff);
bool writeFlash(unsigned addr, uint32_t byteCount, uint8_t writeCmd = 0xff);
/* PS QSPI functions */
void initQSpiPS();
void abortQSpiPS();
void resetQSpiPS();
bool waitGenFifoEmpty();
bool waitTxEmpty();
int writeReg(unsigned regOffset, unsigned value);
bool enterOrExitFourBytesMode(uint32_t enable);
uint32_t readReg(unsigned RegOffset);
uint32_t selectSpiMode(uint8_t SpiMode);
bool setWriteEnable();
void readRxFifo(xqspips_msg_t *msg, int32_t Size);
void fillTxFifo(xqspips_msg_t *msg, int32_t Size);
void setupTXRX(xqspips_msg_t *msg, uint32_t *GenFifoEntry);
void sendGenFifoEntryCSAssert();
void sendGenFifoEntryData(xqspips_msg_t *msg);
void sendGenFifoEntryCSDeAssert();
bool finalTransfer(xqspips_msg_t *msg, uint32_t numMsg);
};
#endif
tools/xbflash.qspi/xspi.cpp
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tools/xbflash.qspi/xspi.h
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/**
* Copyright (C) 2020 Xilinx, Inc
*
* Licensed under the Apache License, Version 2.0 (the "License"). You may
* not use this file except in compliance with the License. A copy of the
* License is located at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*/
#ifndef _XSPI_H_
#define _XSPI_H_
#include <list>
#include "pcidev.h"
#define INVALID_OFFSET ((size_t)-1)
class XSPI_Flasher
{
struct ELARecord
{
unsigned mStartAddress;
unsigned mEndAddress;
unsigned mDataCount;
std::streampos mDataPos;
ELARecord() : mStartAddress(0), mEndAddress(0), mDataCount(0), mDataPos(0) {}
};
typedef std::list<ELARecord> ELARecordList;
ELARecordList recordList;
public:
XSPI_Flasher(pcidev::pci_device *dev, bool dualQSPI);
~XSPI_Flasher();
int xclUpgradeFirmware1(std::istream& mcsStream1);
int xclUpgradeFirmware2(std::istream& mcsStream1, std::istream& mcsStream2);
int revertToMFG(void);
private:
pcidev::pci_device *mDev;
std::FILE *mFlashDev = nullptr;
bool mDualQSPI;
int parseMCS(std::istream& mcsStream);
size_t flash_base;
int xclTestXSpi(int device_index);
unsigned readReg(unsigned offset);
int writeReg(unsigned regOffset, unsigned value);
bool waitTxEmpty();
int macronixConfigure();
bool isFlashReady();
bool sectorErase(unsigned Addr, unsigned erase_cmd);
bool writeBitstreamGuard(unsigned Addr);
bool clearBitstreamGuard(unsigned Addr);
bool bulkErase();
bool writeEnable();
bool getFlashId();
bool finalTransfer(uint8_t *sendBufPtr, uint8_t *recvBufPtr, int byteCount);
bool writePage(unsigned addr, uint8_t writeCmd = 0xff);
bool readPage(unsigned addr, uint8_t readCmd = 0xff);
bool prepareXSpi(uint8_t slave_sel);
int programRecord(std::istream& mcsStream, const ELARecord& record);
int programXSpi(std::istream& mcsStream, uint32_t bitstream_shift_addr);
bool readRegister(unsigned commandCode, unsigned bytes);
bool writeRegister(unsigned commandCode, unsigned value, unsigned bytes);
bool setSector(unsigned address);
unsigned getSector(unsigned address);
// Upgrade firmware via driver.
int upgradeFirmware1Drv(std::istream& mcsStream1);
int upgradeFirmware2Drv(std::istream& mcsStream1, std::istream& mcsStream2);
};
#endif