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PCIe driver: add check of REG_MAP bit in CMS after startup

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leonarski_f
2023-11-18 16:05:43 +01:00
parent 7d48c5f2cd
commit b7e09f20ac
2 changed files with 20 additions and 0 deletions
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fpga/pcie_driver/jfjoch_drv.h
+1
View File
@@ -74,6 +74,7 @@
#define ADDR_CMS_3V3_PEX_INS_REG 0x028034 // in mV
#define ADDR_CMS_HBM_TEMP1_INS_REG 0x028268 // in C
#define ADDR_CMS_HBM_TEMP2_INS_REG 0x0282BC // in C
#define ADDR_CMS_HOST_STATUS2_REG 0x02830C
struct jfjoch_buf {
dma_addr_t dma_address;
fpga/pcie_driver/jfjoch_function.c
+19
View File
@@ -228,8 +228,27 @@ void jfjoch_is_idle(struct jfjoch_drvdata *drvdata, uint32_t *output) {
}
void jfjoch_setup_cms(struct jfjoch_drvdata *drvdata) {
struct device *const dev = &drvdata->pdev->dev;
u32 reg_map_ready, i;
iowrite32(0x1, drvdata->bar0 + CMS_OFFSET + ADDR_CMS_MB_RESETN_REG);
iowrite32(1 << 27, drvdata->bar0 + CMS_OFFSET + ADDR_CMS_CONTROL_REG); // enable HBM monitoring
reg_map_ready = ioread32(drvdata->bar0 + CMS_OFFSET + ADDR_CMS_HOST_STATUS2_REG) & 0x1;
i = 0;
while (i < 10000) {
if (reg_map_ready)
break;
msleep(1);
reg_map_ready = ioread32(drvdata->bar0 + CMS_OFFSET + ADDR_CMS_HOST_STATUS2_REG) & 0x1;
i++;
}
if (i == 10000)
dev_err(dev, "CMS not ready after 10s");
else
dev_info(dev, "CMS ready after restart in %d ms", i);
}
void jfjoch_setup_network(struct jfjoch_drvdata *drvdata) {