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FPGA: Fix pixel_threshold_tb

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leonarski_f
2025-10-03 19:00:46 +02:00
parent 9ed6b6c3c7
commit a074cc3312
2 changed files with 8 additions and 6 deletions
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13
fpga/hls_tb/pixel_threshold_tb.cpp
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@@ -4,7 +4,8 @@
#include "../hls_simulation/hls_cores.h"
int main() {
int32_t threshold = 32;
int32_t min_threshold = 16;
int32_t max_threshold = 30;
bool all_good = true;
@@ -15,13 +16,13 @@ int main() {
packet_in.user = 0;
packet_in.data = 0;
ACT_REG_THRESHOLD(packet_in.data) = threshold;
ACT_REG_MODE(packet_in.data) = MODE_THRESHOLD;
ACT_REG_THRESHOLD_MIN(packet_in.data) = min_threshold;
ACT_REG_THRESHOLD_MAX(packet_in.data) = max_threshold;
input << packet_in;
ap_int<24> values_in[32], values_out[32];
for (int i = 0; i < 30; i++)
for (int i = 0; i < 29; i++)
values_in[i] = i;
values_in[30] = INT24_MAX;
@@ -45,8 +46,10 @@ int main() {
if (values_in[i] == INT24_MIN)
value_expected = INT24_MIN;
else if (values_in[i] < threshold)
else if (values_in[i] < min_threshold)
value_expected = 0;
else if (values_in[i] > max_threshold)
value_expected = INT24_MAX;
if (values_out[i] != value_expected) {
all_good = false;

1
fpga/pcie_driver/jfjoch_fpga.h
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@@ -37,7 +37,6 @@ typedef __u64 uint64_t;
#define MODE_EIGER_32BIT 0x0010L
#define MODE_EIGER_8BIT 0x0020L
#define MODE_FIXG1 0x0080L
#define MODE_THRESHOLD 0x0100L
#define MODE_8BIT_OUTPUT 0x0200L
#define MODE_APPLY_PIXEL_MASK 0x0400L