FPGA: spot_finder added
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@@ -75,6 +75,7 @@ inline ap_uint<1> read_request(hls::stream<ap_uint<32> > &s_axis_work_request,
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void host_writer(STREAM_512 &data_in,
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hls::stream<ap_uint<192>> &integration_in,
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hls::stream<ap_uint<512>> &spot_finder_in,
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hls::stream<axis_completion > &s_axis_completion,
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hls::stream<ap_axiu<512,1,1,1> > &host_memory_out,
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hls::stream<axis_datamover_ctrl> &datamover_out_cmd,
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@@ -86,6 +87,7 @@ void host_writer(STREAM_512 &data_in,
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#pragma HLS INTERFACE ap_ctrl_none port=return
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#pragma HLS INTERFACE register both axis port=data_in
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#pragma HLS INTERFACE register both axis port=integration_in
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#pragma HLS INTERFACE register both axis port=spot_finder_in
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#pragma HLS INTERFACE register both axis port=s_axis_completion
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#pragma HLS INTERFACE register both axis port=host_memory_out
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#pragma HLS INTERFACE register both axis port=datamover_out_cmd
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@@ -124,8 +126,8 @@ void host_writer(STREAM_512 &data_in,
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s_axis_completion >> cmpl;
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while (!cmpl.last) {
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read_request(s_axis_work_request, req_handle, req_host_offset);
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setup_datamover(datamover_out_cmd, req_host_offset, RAW_MODULE_SIZE * sizeof(uint16_t)
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+ (FPGA_INTEGRATION_BIN_COUNT)*64);
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setup_datamover(datamover_out_cmd, req_host_offset,
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RAW_MODULE_SIZE * sizeof(uint16_t) * (16 + 1) / 16 + (FPGA_INTEGRATION_BIN_COUNT)*64);
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packet_512_t packet_out;
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packet_out.strb = UINT64_MAX;
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@@ -142,6 +144,12 @@ void host_writer(STREAM_512 &data_in,
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host_memory_out << packet_out;
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}
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for (int i = 0; i < RAW_MODULE_SIZE * sizeof(uint16_t) / (64 * 16); i++) {
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#pragma HLS PIPELINE II=1
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spot_finder_in >> packet_out.data;
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host_memory_out << packet_out;
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}
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for (int i = 0; i < FPGA_INTEGRATION_BIN_COUNT; i++) {
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#pragma HLS PIPELINE II=1
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ap_uint<192> tmp;
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