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FPGA: Add bitshuffle to the design (warning! no test for full integration!)

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This commit is contained in:
leonarski_f
2023-10-25 11:07:21 +02:00
parent a611d3f08b
commit 6bcf54f603
3 changed files with 28 additions and 11 deletions
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receiver/HLSSimulatedDevice.cpp
+7 -2
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@@ -230,6 +230,7 @@ void HLSSimulatedDevice::HLSMainThread() {
STREAM_512 converted_7;
STREAM_512 converted_8;
STREAM_512 converted_9;
STREAM_512 converted_10;
hls::stream<axis_addr> addr0;
hls::stream<axis_addr> addr1;
@@ -358,14 +359,18 @@ void HLSSimulatedDevice::HLSMainThread() {
hls_cores.emplace_back([&] { axis_128_to_512(integration_result_0, integration_result_1);});
// 8. Extend multipixels
hls_cores.emplace_back([&] { add_multipixel(converted_7, converted_8);});
// 9. Apply bitshuffle
hls_cores.emplace_back([&] { bitshuffle(converted_8, converted_9);});
// Timer procedure - count how many times write_data is not accepting input (to help track down latency issues)
hls_cores.emplace_back([&] { timer_host(converted_8, converted_9, counter_host); });
hls_cores.emplace_back([&] { timer_host(converted_9, converted_10, counter_host); });
// 8. Prepare data to write to host memory
hls_cores.emplace_back([&] {
host_writer(converted_9, adu_histo_result, integration_result_1, spot_finder_result_1,
host_writer(converted_10, adu_histo_result, integration_result_1, spot_finder_result_1,
compl5, datamover_out.GetDataStream(),
datamover_out.GetCtrlStream(), work_request_stream, completion_stream,
packets_processed, host_writer_idle, err_reg); });