FPGA: Do not load internal packet generator frame via DMA

receiver/HLSSimulatedDevice.cpp

@@ -51,8 +51,6 @@ HLSSimulatedDevice::HLSSimulatedDevice(uint16_t data_stream, size_t in_frame_buf
     for (auto &i: hbm_memory)
         // i.resize(SIZE_OF_HBM_BLOCK_IN_BYTES);
         i.resize(32*1024*1024); // only 32 MiB instead of 256 MiB per HBM interface (should be more than enough for all the tests anyway)
-
-    internal_packet_generator_uram.resize(RAW_MODULE_SIZE * sizeof(uint16_t) / 512 * 8);
 }
 
 void HLSSimulatedDevice::CreateFinalPacket(const DiffractionExperiment& experiment) {
@@ -291,7 +289,8 @@ void HLSSimulatedDevice::HLSMainThread() {
                                                   calibration_addr_bram); });
 
     // Generate internal packets
-    hls_cores.emplace_back([&] { internal_packet_generator(raw2, raw3, addr1, addr2, internal_packet_generator_uram.data(),
+    hls_cores.emplace_back([&] { internal_packet_generator(raw2, raw3, addr1, addr2,
+                                                           reinterpret_cast<ap_uint<512> *>(internal_pkt_gen_frame.data()),
                                                            cancel_data_collection); });
 
     // Timer procedure - count how many times pedestal_corr/gain_corr is not accepting input (to help track down latency issues)