linse/frappy
0
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Driver and cfg file for ac resistance bridge

Browse Source 
Change-Id: I77b2294b57315fcf7d94996a2a68fcac72866710
This commit is contained in:
Oksana Shliakhtun 2024-05-06 11:57:50 +02:00 committed by Markus Zolliker
parent a5e698163b
commit c20801c8fe
2 changed files with 81 additions and 55 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

32
cfg/SIM921_cfg.py Normal file
View File

@ -0,0 +1,32 @@
Node('bridge.psi.ch',
'ac resistance bridge',
'tcp://5000'
)
Mod('io',
'frappy_psi.bridge.BridgeIO',
'communication to sim900',
uri='serial:///dev/cu.usbserial-21440'
)
# Mod('SIM921_A',
# 'frappy_psi.bridge.SIM921',
# 'module communication',
# io='io',
# channel='A'
# )
# Mod('SIM921_B',
# 'frappy_psi.bridge.SIM921',
# 'module communication',
# io='io',
# channel='B'
# )
#
# Mod('SIM921_C',
# 'frappy_psi.bridge.SIM921',
# 'module communication',
# io='io',
# channel='C'
# )

104
frappy_psi/bridge.py
View File

@ -18,7 +18,8 @@
import re
from frappy.core import HasIO, Readable, Drivable, Parameter, FloatRange, IntRange, EnumType, \
Enum
Enum, Property, StringType
from SR830 import string_to_value
class BridgeIO(HasIO):
@ -29,54 +30,62 @@ class BridgeIO(HasIO):
self.communicate(f'conn {port}')
return self.communicate(f'send {port}, "{cmd}\r"')
def set_par(self, cmd, *args):
head = ','.join([cmd] + [a if isinstance(a, str) else f'{a:g}' for a in args])
tail = cmd.replace(' ', '? ')
new_tail = re.sub(r'[0-9.]+', '', tail)
reply = self.comm(f'{head};{new_tail}')
result = []
for num in reply.split(','):
try:
result.append(float(num))
except ValueError:
result.append(num)
if len(result) == 1:
return result[0]
return result
def get_par(self, cmd):
reply = self.comm(cmd)
result = []
for num in reply.split(','):
try:
result.append(float(num))
except ValueError:
result.append(num)
if len(result) == 1:
return result[0]
return result
# def set_par(self, cmd, *args):
# head = ','.join([cmd] + [a if isinstance(a, str) else f'{a:g}' for a in args])
# tail = cmd.replace(' ', '? ')
# new_tail = re.sub(r'[0-9.]+', '', tail)
#
# reply = self.comm(f'{head};{new_tail}')
# result = []
# for num in reply.split(','):
# try:
# result.append(float(num))
# except ValueError:
# result.append(num)
# if len(result) == 1:
# return result[0]
# return result
#
# def get_par(self, cmd):
# reply = self.comm(cmd)
# result = []
# for num in reply.split(','):
# try:
# result.append(float(num))
# except ValueError:
# result.append(num)
# if len(result) == 1:
# return result[0]
# return result
class SIM921(BridgeIO, Readable, Drivable):
#port = Parameter()
value = Parameter('temperature', unit='K')
channel = Property('sim921 module', StringType())
setpoint = Parameter('temperature deviation', datatype=FloatRange, unit='K')
resistance = Parameter('resistance', datatype=FloatRange, unit='ohm')
irange = Parameter('resistance range index', IntRange)
value = Parameter('resistance', datatype=FloatRange, unit='ohm')
dev = Property('resistance deviation', FloatRange())
RES_RANGE = ['20mOhm', '200mOhm', '2Ohm', '20Ohm', '200Ohm', '2kOhm', '20kOhm', '200kOhm',
'2MOhm', '20MOhm']
irange = Parameter('range index', EnumType('resistance range index',
{name: idx for idx, name in enumerate(RES_RANGE)}), readonly=False)
phase = Parameter('phase', FloatRange, unit='ang')
tc = Parameter('time constant', FloatRange)
TIME_CONST = ['0.3s', '1s', '3s', '10s', '30s', '100s', '300s']
tc = Parameter('time constant value', FloatRange(1e-1, 3e2), unit='s', readonly=False)
itc = Parameter('time constant index',
EnumType('time const. index range',
{name: value for value, name in enumerate(TIME_CONST)}), readonly=False)
autorange = Parameter('autorange_on', EnumType('autorange', off=0, soft=1, hard=2),
readonly=False, default=0)
ioClass = BridgeIO
def read_resistance(self):
return self.get_par('rval')
def read_value(self):
return self.get_par('tval')
return self.get_par('rval?')
def read_phase(self):
return self.get_par('phase')
@ -93,23 +102,8 @@ class SIM921(BridgeIO, Readable, Drivable):
def write_tc(self, tc):
return self.set_par(f'tcon {tc}')
def read_dev(self):
return self.comm('rdev?')