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Merged devlib2mmio branch

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This commit is contained in:
Andrew Johnson
2014-09-26 14:28:28 -05:00
parent abc3417623 59a0fa9364
commit 5ae6dd3a7c
9 changed files with 633 additions and 65 deletions
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documentation/RELEASE_NOTES.html
+9
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@@ -15,6 +15,15 @@ EPICS Base 3.15.0.x releases are not intended for use in production systems.</p>
<h2 align="center">Changes between 3.15.0.1 and 3.15.0.2</h2>
<!-- Insert new items immediately below here ... -->
<h3>Merge MMIO API from devLib2</h3>
<p>Added calls to handle 8, 16, and 32 bit Memory Mapped I/O reads and writes.
The calls added include <tt><i>X</i>_iowrite<i>Y</i>()</tt> and
<tt><i>X</i>_ioread<i>Y</i>()</tt>
where <tt><i>X</i></tt> is <tt>nat</tt> (native), <tt>be</tt> or <tt>le</tt>,
and <tt><i>Y</i></tt> is <tt>16</tt> or <tt>32</tt>.
Also added are <tt>ioread8()</tt> and <tt>iowrite8()</tt>.</p>
<h3>Added optional dbServer API to database</h3>
<p>A server layer that sits on top of the IOC database may now register itself
src/libCom/osi/Makefile
+2
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@@ -62,6 +62,8 @@ INC += devLib.h
INC += devLibVME.h
INC += devLibVMEImpl.h
INC += osdVME.h
INC += epicsMMIO.h
INC += epicsMMIODef.h
Com_SRCS += epicsThread.cpp
Com_SRCS += epicsMutex.cpp
src/libCom/osi/os/RTEMS/epicsMMIO.h
+58
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@@ -0,0 +1,58 @@
/*************************************************************************\
* Copyright (c) 2010 Brookhaven Science Associates, as Operator of
* Brookhaven National Laboratory.
* EPICS BASE is distributed subject to a Software License Agreement found
* in file LICENSE that is included with this distribution.
\*************************************************************************/
/*
* Author: Michael Davidsaver <mdavidsaver@bnl.gov>
*/
#ifndef EPICSMMIO_H
#define EPICSMMIO_H
#include <epicsEndian.h>
#if defined(_ARCH_PPC) || defined(__PPC__) || defined(__PPC)
# include <libcpu/io.h>
/*NOTE: All READ/WRITE operations have an implicit read or write barrier */
# define ioread8(A) in_8((volatile epicsUInt8*)(A))
# define iowrite8(A,D) out_8((volatile epicsUInt8*)(A), D)
# define le_ioread16(A) in_le16((volatile epicsUInt16*)(A))
# define le_ioread32(A) in_le32((volatile epicsUInt32*)(A))
# define le_iowrite16(A,D) out_le16((volatile epicsUInt16*)(A), D)
# define le_iowrite32(A,D) out_le32((volatile epicsUInt32*)(A), D)
# define be_ioread16(A) in_be16((volatile epicsUInt16*)(A))
# define be_ioread32(A) in_be32((volatile epicsUInt32*)(A))
# define be_iowrite16(A,D) out_be16((volatile epicsUInt16*)(A), D)
# define be_iowrite32(A,D) out_be32((volatile epicsUInt32*)(A), D)
# define rbarr() iobarrier_r()
# define wbarr() iobarrier_w()
# define rwbarr() iobarrier_rw()
/* Define native operations */
# define nat_ioread16 be_ioread16
# define nat_ioread32 be_ioread32
# define nat_iowrite16 be_iowrite16
# define nat_iowrite32 be_iowrite32
#elif defined(i386) || defined(__i386__) || defined(__i386) || defined(__m68k__)
/* X86 does not need special handling for read/write width.
*
* TODO: Memory barriers?
*/
#include "epicsMMIODef.h"
#else
# warning I/O operations not defined for this RTEMS architecture
#include "epicsMMIODef.h"
#endif /* if defined PPC */
#endif /* EPICSMMIO_H */
src/libCom/osi/os/default/epicsMMIO.h
+2
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@@ -0,0 +1,2 @@
#include "epicsMMIODef.h"
src/libCom/osi/os/default/epicsMMIODef.h
+268
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@@ -0,0 +1,268 @@
/*************************************************************************\
* Copyright (c) 2010 Brookhaven Science Associates, as Operator of
* Brookhaven National Laboratory.
* EPICS BASE is distributed subject to a Software License Agreement found
* in file LICENSE that is included with this distribution.
\*************************************************************************/
/*
* Author: Michael Davidsaver <mdavidsaver@bnl.gov>
*/
#ifndef EPICSMMIODEF_H
#define EPICSMMIODEF_H
#include <epicsTypes.h>
#include <epicsEndian.h>
#include <shareLib.h>
#ifdef __cplusplus
# ifndef INLINE
# define INLINE inline
# endif
#endif
/** @ingroup mmio
*@{
*/
/** @brief Read a single byte.
*/
INLINE
epicsUInt8
ioread8(volatile void* addr)
{
return *(volatile epicsUInt8*)(addr);
}
/** @brief Write a single byte.
*/
INLINE
void
iowrite8(volatile void* addr, epicsUInt8 val)
{
*(volatile epicsUInt8*)(addr) = val;
}
/** @brief Read two bytes in host order.
* Not byte swapping
*/
INLINE
epicsUInt16
nat_ioread16(volatile void* addr)
{
return *(volatile epicsUInt16*)(addr);
}
/** @brief Write two byte in host order.
* Not byte swapping
*/
INLINE
void
nat_iowrite16(volatile void* addr, epicsUInt16 val)
{
*(volatile epicsUInt16*)(addr) = val;
}
/** @brief Read four bytes in host order.
* Not byte swapping
*/
INLINE
epicsUInt32
nat_ioread32(volatile void* addr)
{
return *(volatile epicsUInt32*)(addr);
}
/** @brief Write four byte in host order.
* Not byte swapping
*/
INLINE
void
nat_iowrite32(volatile void* addr, epicsUInt32 val)
{
*(volatile epicsUInt32*)(addr) = val;
}
#if EPICS_BYTE_ORDER == EPICS_ENDIAN_BIG
/** @ingroup mmio
*@{
*/
#define bswap16(value) ((epicsUInt16) ( \
(((epicsUInt16)(value) & 0x00ff) << 8) | \
(((epicsUInt16)(value) & 0xff00) >> 8)))
#define bswap32(value) ( \
(((epicsUInt32)(value) & 0x000000ff) << 24) | \
(((epicsUInt32)(value) & 0x0000ff00) << 8) | \
(((epicsUInt32)(value) & 0x00ff0000) >> 8) | \
(((epicsUInt32)(value) & 0xff000000) >> 24))
# define be_ioread16(A) nat_ioread16(A)
# define be_ioread32(A) nat_ioread32(A)
# define be_iowrite16(A,D) nat_iowrite16(A,D)
# define be_iowrite32(A,D) nat_iowrite32(A,D)
# define le_ioread16(A) bswap16(nat_ioread16(A))
# define le_ioread32(A) bswap32(nat_ioread32(A))
# define le_iowrite16(A,D) nat_iowrite16(A,bswap16(D))
# define le_iowrite32(A,D) nat_iowrite32(A,bswap32(D))
/** @} */
#elif EPICS_BYTE_ORDER == EPICS_ENDIAN_LITTLE
#include <arpa/inet.h>
#ifdef __rtems__
/* some rtems bsps (pc386) don't provide htonl correctly */
# include <rtems/endian.h>
#endif
/** @ingroup mmio
*@{
*/
/* hton* is optimized or a builtin for most compilers
* so use it if possible
*/
#define bswap16(v) htons(v)
#define bswap32(v) htonl(v)
# define be_ioread16(A) bswap16(nat_ioread16(A))
# define be_ioread32(A) bswap32(nat_ioread32(A))
# define be_iowrite16(A,D) nat_iowrite16(A,bswap16(D))
# define be_iowrite32(A,D) nat_iowrite32(A,bswap32(D))
# define le_ioread16(A) nat_ioread16(A)
# define le_ioread32(A) nat_ioread32(A)
# define le_iowrite16(A,D) nat_iowrite16(A,D)
# define le_iowrite32(A,D) nat_iowrite32(A,D)
/** @} */
#else
# error Unable to determine native byte order
#endif
/** @def bswap16
* @brief Unconditional two byte swap
*/
/** @def bswap32
* @brief Unconditional four byte swap
*/
/** @def be_ioread16
* @brief Read two byte in big endian order.
*/
/** @def be_iowrite16
* @brief Write two byte in big endian order.
*/
/** @def be_ioread32
* @brief Read four byte in big endian order.
*/
/** @def be_iowrite32
* @brief Write four byte in big endian order.
*/
/** @def le_ioread16
* @brief Read two byte in little endian order.
*/
/** @def le_iowrite16
* @brief Write two byte in little endian order.
*/
/** @def le_ioread32
* @brief Read four byte in little endian order.
*/
/** @def le_iowrite32
* @brief Write four byte in little endian order.
*/
/** @ingroup mmio
*@{
*/
/** @brief Explicit read memory barrier
* Prevents reordering of reads around it.
*/
#define rbarr() do{}while(0)
/** @brief Explicit write memory barrier
* Prevents reordering of writes around it.
*/
#define wbarr() do{}while(0)
/** @brief Explicit read/write memory barrier
* Prevents reordering of reads or writes around it.
*/
#define rwbarr() do{}while(0)
/** @} */
/** @defgroup mmio Memory Mapped I/O
*
* Safe operations on I/O memory.
*
*This files defines a set of macros for access to Memory Mapped I/O
*
*They are named T_ioread# and T_iowrite# where # can be 8, 16, or 32.
*'T' can either be 'le', 'be', or 'nat' (except ioread8 and
*iowrite8).
*
*The macros defined use OS specific extensions (when available)
*to ensure the following.
*
*@li Width. A 16 bit operation will not be broken into two 8 bit operations,
* or one half of a 32 bit operation.
*
*@li Order. Writes to two different registers will not be reordered.
* This only applies to MMIO operations, not between MMIO and
* normal memory operations.
*
*PCI access should use either 'le_' or 'be_' as determined by the
*device byte order.
*
*VME access should always use 'nat_'. If the device byte order is
*little endian then an explicit swap is required.
*
*@section mmioex Examples:
*
*@subsection mmioexbe Big endian device:
*
*@b PCI
*
@code
be_iowrite16(base+off, 14);
var = be_ioread16(base+off);
@endcode
*
*@b VME
*
@code
nat_iowrite16(base+off, 14);
var = nat_ioread16(base+off);
@endcode
*
*@subsection mmioexle Little endian device
*
*@b PCI
@code
le_iowrite16(base+off, 14);
var = le_ioread16(base+off);
@endcode
*@b VME
@code
nat_iowrite16(base+off, bswap16(14));
var = bswap16(nat_iowrite16(base+off));
@endcode
*This difference arises because VME bridges implement hardware byte
*swapping on little endian systems, while PCI bridges do not.
*Software accessing PCI devices must know if byte swapping is required.
*This conditional swap is implemented by the 'be_' and 'le_' macros.
*
*This is a fundamental difference between PCI and VME.
*
*Software accessing PCI @b must do conditional swapping.
*
*Software accessing VME must @b not do conditional swapping.
*
*@note All read and write operations have an implicit read or write barrier.
*/
#endif /* EPICSMMIODEF_H */
src/libCom/osi/os/vxWorks/epicsMMIO.h
+160
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@@ -0,0 +1,160 @@
/*************************************************************************\
* Copyright (c) 2014 Brookhaven Science Associates, as Operator of
* Brookhaven National Laboratory.
* Copyright (c) 2014 UChicago Argonne LLC, as Operator of Argonne
* National Laboratory.
* Copyright (c) 2006 The Regents of the University of California,
* as Operator of Los Alamos National Laboratory.
* Copyright (c) 2006 The Board of Trustees of the Leland Stanford Junior
* University, as Operator of the Stanford Linear Accelerator Center.
* EPICS BASE is distributed subject to a Software License Agreement found
* in file LICENSE that is included with this distribution.
\*************************************************************************/
/*
* Original Author: Eric Bjorklund (was called mrfSyncIO.h)
* Author: Michael Davidsaver <mdavidsaver@bnl.gov>
*/
#ifndef EPICSMMIO_H
#define EPICSMMIO_H
#if (CPU_FAMILY != PPC) && (CPU_FAMILY != I80X86)
# include "epicsMMIODef.h"
#else
/**************************************************************************************************/
/* Required Header Files */
/**************************************************************************************************/
/* This is needed on vxWorks 6.8 */
#ifndef _VSB_CONFIG_FILE
# define _VSB_CONFIG_FILE <../lib/h/config/vsbConfig.h>
#endif
#include <vxWorks.h> /* vxWorks common definitions */
#include <sysLib.h> /* vxWorks System Library Definitions */
#include <version.h> /* vxWorks Version Definitions */
#include <epicsTypes.h> /* EPICS Common Type Definitions */
#include <epicsEndian.h> /* EPICS Byte Order Definitions */
/*=====================
* vxAtomicLib.h (which defines the memory barrier macros)
* is available on vxWorks 6.6 and above.
*/
#if _WRS_VXWORKS_MAJOR > 6
# include <vxAtomicLib.h>
#elif _WRS_VXWORKS_MAJOR == 6 && _WRS_VXWORKS_MINOR >= 6
# include <vxAtomicLib.h>
#endif
#define bswap16(value) ((epicsUInt16) ( \
(((epicsUInt16)(value) & 0x00ff) << 8) | \
(((epicsUInt16)(value) & 0xff00) >> 8)))
#define bswap32(value) ( \
(((epicsUInt32)(value) & 0x000000ff) << 24) | \
(((epicsUInt32)(value) & 0x0000ff00) << 8) | \
(((epicsUInt32)(value) & 0x00ff0000) >> 8) | \
(((epicsUInt32)(value) & 0xff000000) >> 24))
#if EPICS_BYTE_ORDER == EPICS_ENDIAN_BIG
# define be16_to_cpu(X) (epicsUInt16)(X)
# define be32_to_cpu(X) (epicsUInt32)(X)
# define le16_to_cpu(X) bswap16(X)
# define le32_to_cpu(X) bswap32(X)
#elif EPICS_BYTE_ORDER == EPICS_ENDIAN_LITTLE
# define be16_to_cpu(X) bswap16(X)
# define be32_to_cpu(X) bswap32(X)
# define le16_to_cpu(X) (epicsUInt16)(X)
# define le32_to_cpu(X) (epicsUInt32)(X)
#else
# error Unable to determine native byte order
#endif
#if CPU_FAMILY == PPC
/* All PowerPC BSPs that I have studied implement these functions
* with the same definition, byte-swapping the data and adding a
* sync and/or eieio instruction as necessary on that CPU board.
* They do *not* all implement the sys{In/Out}{Byte/Word/Long}
* functions to do the same thing though, so we can't use them.
*/
UINT8 sysPciInByte(UINT8 *addr);
void sysPciOutByte(UINT8 *addr, UINT8 data);
UINT16 sysPciInWord(UINT16 *addr);
void sysPciOutWord(UINT16 *addr, UINT16 data);
UINT32 sysPciInLong (UINT32 *addr);
void sysPciOutLong (UINT32 *addr, UINT32 data);
#define ioread8(address) sysPciInByte((UINT8 *)(address))
#define iowrite8(address,data) sysPciOutByte((UINT8 *)(address), (epicsUInt8)(data))
#define nat_ioread16(address) bswap16(sysPciInWord((UINT16 *)(address)))
#define nat_ioread32(address) bswap32(sysPciInLong((UINT32 *)(address)))
#define nat_iowrite16(address,data) sysPciOutWord((UINT16 *)(address), bswap16(data))
#define nat_iowrite32(address,data) sysPciOutLong((UINT32 *)(address), bswap32(data))
#define be_ioread16(address) bswap16(sysPciInWord((UINT16 *)(address)))
#define be_ioread32(address) bswap32(sysPciInLong((UINT32 *)(address)))
#define be_iowrite16(address,data) sysPciOutWord((UINT16 *)(address), bswap16(data))
#define be_iowrite32(address,data) sysPciOutLong((UINT32 *)(address), bswap32(data))
#define le_ioread16(address) sysPciInWord((UINT16 *)(address))
#define le_ioread32(address) sysPciInLong((UINT32 *)(address))
#define le_iowrite16(address,data) sysPciOutWord((UINT16 *)(address), (data))
#define le_iowrite32(address,data) sysPciOutLong((UINT32 *)(address), (data))
#else /* CPU_FAMILY == I80X86 */
/* All Intel BSPs should implement the sys{In/Out}{Byte/Word/Long}
* functions, which are declared in the sysLib.h header.
*/
#define ioread8(address) sysInByte ((epicsUInt32)(address))
#define iowrite8(address,data) sysOutByte ((epicsUInt32)(address), (epicsUInt8)(data))
#define nat_ioread16(address) sysInWord ((epicsUInt32)(address))
#define nat_ioread32(address) sysInLong ((epicsUInt32)(address))
#define nat_iowrite16(address,data) sysOutWord((epicsUInt32)(address),(data))
#define nat_iowrite32(address,data) sysOutLong((epicsUInt32)(address),(data))
#define be_ioread16(address) be16_to_cpu (sysInWord ((epicsUInt32)(address)))
#define be_ioread32(address) be32_to_cpu (sysInLong ((epicsUInt32)(address)))
#define be_iowrite16(address,data) sysOutWord ((epicsUInt32)(address), be16_to_cpu((epicsUInt16)(data)))
#define be_iowrite32(address,data) sysOutLong ((epicsUInt32)(address), be32_to_cpu((epicsUInt32)(data)))
#define le_ioread16(address) le16_to_cpu (sysInWord ((epicsUInt32)(address)))
#define le_ioread32(address) le32_to_cpu (sysInLong ((epicsUInt32)(address)))
#define le_iowrite16(address,data) sysOutWord ((epicsUInt32)(address), le16_to_cpu((epicsUInt16)(data)))
#define le_iowrite32(address,data) sysOutLong ((epicsUInt32)(address), le32_to_cpu((epicsUInt32)(data)))
#endif /* I80X86 */
#ifndef VX_MEM_BARRIER_R
# define VX_MEM_BARRIER_R() do{}while(0)
#endif
#ifndef VX_MEM_BARRIER_W
# define VX_MEM_BARRIER_W() do{}while(0)
#endif
#ifndef VX_MEM_BARRIER_RW
# define VX_MEM_BARRIER_RW() do{}while(0)
#endif
#define rbarr() VX_MEM_BARRIER_R()
#define wbarr() VX_MEM_BARRIER_W()
#define rwbarr() VX_MEM_BARRIER_RW()
#endif /* CPU_FAMILY */
#endif /* EPICSMMIO_H */
src/libCom/test/Makefile
+5
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@@ -37,6 +37,11 @@ epicsMathTest_SRCS += epicsMathTest.c
testHarness_SRCS += epicsMathTest.c
TESTS += epicsMathTest
TESTPROD_HOST += epicsMMIOTest
epicsMMIOTest_SRCS += epicsMMIOTest.c
testHarness_SRCS += epicsMMIOTest.c
TESTS += epicsMMIOTest
TESTPROD_HOST += epicsEllTest
epicsEllTest_SRCS += epicsEllTest.c
testHarness_SRCS += epicsEllTest.c
src/libCom/test/epicsMMIOTest.c
+87
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@@ -0,0 +1,87 @@
/*************************************************************************\
* Copyright (c) 2013 Brookhaven Science Associates, as Operator of
* Brookhaven National Laboratory.
* EPICS BASE is distributed subject to a Software License Agreement found
* in file LICENSE that is included with this distribution.
\*************************************************************************/
/*
* Author: Michael Davidsaver <mdavidsaver@bnl.gov>
*/
#include "epicsAssert.h"
#include "epicsEndian.h"
#include "epicsTypes.h"
#include "epicsUnitTest.h"
#include "testMain.h"
#include "epicsMMIO.h"
#if EPICS_BYTE_ORDER==EPICS_ENDIAN_BIG
#define BE16 0x1234
#define BE32 0x12345678
#define LE16 0x3412
#define LE32 0x78563412
#else
#define LE16 0x1234
#define LE32 0x12345678
#define BE16 0x3412
#define BE32 0x78563412
#endif
union hydra16 {
epicsUInt16 u16;
epicsUInt8 bytes[2];
};
union hydra32 {
epicsUInt32 u32;
epicsUInt8 bytes[4];
};
MAIN(epicsMMIOTest)
{
epicsUInt8 B;
union hydra16 H16;
union hydra32 H32;
STATIC_ASSERT(sizeof(H16)==2);
STATIC_ASSERT(sizeof(H32)==4);
testPlan(0);
testDiag("8-bit ops");
iowrite8(&B, 5);
testOk1(B==5);
testOk1(ioread8(&B)==5);
testDiag("16-bit ops");
nat_iowrite16(&H16.bytes, 0x1234);
testOk1(H16.u16==0x1234);
testOk1(nat_ioread16(&H16.bytes)==0x1234);
be_iowrite16(&H16.bytes, 0x1234);
testOk1(H16.u16==BE16);
testOk1(be_ioread16(&H16.bytes)==0x1234);
le_iowrite16(&H16.bytes, 0x1234);
testOk1(H16.u16==LE16);
testOk1(le_ioread16(&H16.bytes)==0x1234);
testDiag("32-bit ops");
nat_iowrite32(&H32.bytes, 0x12345678);
testOk1(H32.u32==0x12345678);
testOk1(nat_ioread32(&H32.bytes)==0x12345678);
be_iowrite32(&H32.bytes, 0x12345678);
testOk1(H32.u32==BE32);
testOk1(be_ioread32(&H32.bytes)==0x12345678);
le_iowrite32(&H32.bytes, 0x12345678);
testOk1(H32.u32==LE32);
testOk1(le_ioread32(&H32.bytes)==0x12345678);
return testDone();
}
src/libCom/test/epicsRunLibComTests.c
+42 -65
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@@ -16,38 +16,39 @@
#include <epicsThread.h>
#include <epicsUnitTest.h>
int epicsThreadTest(void);
int epicsTimerTest(void);
int epicsSpinTest(void);
int blockingSockTest(void);
int epicsAlgorithm(void);
int epicsCalcTest(void);
int epicsEllTest(void);
int epicsEnvTest(void);
int epicsErrlogTest(void);
int epicsCalcTest(void);
int epicsEventTest(void);
int epicsExceptionTest(void);
int epicsExitTest(void);
int epicsMathTest(void);
int epicsMessageQueueTest(void);
int epicsMMIOTest(void);
int epicsMutexTest(void);
int epicsSockResolveTest(void);
int epicsSpinTest(void);
int epicsStackTraceTest(void);
int epicsStdioTest(void);
int epicsStdlibTest(void);
int epicsStringTest(void);
int epicsThreadHooksTest(void);
int epicsThreadOnceTest(void);
int epicsThreadPoolTest(void);
int epicsThreadPriorityTest(void);
int epicsThreadPrivateTest(void);
int epicsThreadHooksTest(void);
int epicsThreadPoolTest(void);
int epicsThreadTest(void);
int epicsTimerTest(void);
int epicsTimeTest(void);
int epicsTypesTest(void);
int macLibTest(void);
int macEnvExpandTest(void);
int ringPointerTest(void);
int macLibTest(void);
int ringBytesTest(void);
int blockingSockTest(void);
int epicsSockResolveTest(void);
int ringPointerTest(void);
int taskwdTest(void);
int epicsExitTest(void);
void epicsRunLibComTests(void)
{
@@ -63,62 +64,38 @@ void epicsRunLibComTests(void)
*/
runTest(epicsTimerTest);
runTest(epicsSpinTest);
runTest(epicsAlgorithm);
runTest(epicsEllTest);
runTest(epicsEnvTest);
runTest(epicsErrlogTest);
runTest(epicsCalcTest);
runTest(epicsEventTest);
runTest(epicsExceptionTest);
runTest(epicsMathTest);
runTest(epicsMessageQueueTest);
runTest(epicsMutexTest);
runTest(epicsStackTraceTest);
runTest(epicsStdioTest);
runTest(epicsStdlibTest);
runTest(epicsStringTest);
runTest(epicsThreadOnceTest);
runTest(epicsThreadPriorityTest);
runTest(epicsThreadPrivateTest);
runTest(epicsThreadHooksTest);
runTest(epicsThreadPoolTest);
runTest(epicsTimeTest);
runTest(epicsTypesTest);
runTest(macLibTest);
runTest(macEnvExpandTest);
runTest(ringPointerTest);
runTest(ringBytesTest);
/*
* Run the regular tests in alphabetical order
*/
runTest(blockingSockTest);
runTest(epicsAlgorithm);
runTest(epicsCalcTest);
runTest(epicsEllTest);
runTest(epicsEnvTest);
runTest(epicsErrlogTest);
runTest(epicsEventTest);
runTest(epicsExceptionTest);
runTest(epicsMathTest);
runTest(epicsMessageQueueTest);
runTest(epicsMMIOTest);
runTest(epicsMutexTest);
runTest(epicsSockResolveTest);
runTest(epicsSpinTest);
runTest(epicsStackTraceTest);
runTest(epicsStdioTest);
runTest(epicsStdlibTest);
runTest(epicsStringTest);
runTest(epicsThreadHooksTest);
runTest(epicsThreadOnceTest);
runTest(epicsThreadPoolTest);
runTest(epicsThreadPriorityTest);
runTest(epicsThreadPrivateTest);
runTest(epicsTimeTest);
runTest(epicsTypesTest);
runTest(macEnvExpandTest);
runTest(macLibTest);
runTest(ringBytesTest);
runTest(ringPointerTest);
runTest(taskwdTest);
/*