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Fix vxWorks again, passes the tests on all my CPUs now.

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This commit is contained in:
Andrew Johnson
2014-08-01 16:06:17 -05:00
parent fcd0a4c75d
commit 59a0fa9364
1 changed files with 54 additions and 8 deletions
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62
src/libCom/osi/os/vxWorks/epicsMMIO.h
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@@ -18,7 +18,7 @@
#ifndef EPICSMMIO_H
#define EPICSMMIO_H
#if CPU_FAMILY == MC680X0
#if (CPU_FAMILY != PPC) && (CPU_FAMILY != I80X86)
# include "epicsMMIODef.h"
#else
@@ -60,21 +60,64 @@
(((epicsUInt32)(value) & 0xff000000) >> 24))
#if EPICS_BYTE_ORDER == EPICS_ENDIAN_BIG
# define be16_to_cpu(X) (X)
# define be32_to_cpu(X) (X)
# define be16_to_cpu(X) (epicsUInt16)(X)
# define be32_to_cpu(X) (epicsUInt32)(X)
# define le16_to_cpu(X) bswap16(X)
# define le32_to_cpu(X) bswap32(X)
#elif EPICS_BYTE_ORDER == EPICS_ENDIAN_LITTLE
# define be16_to_cpu(X) bswap16(X)
# define be32_to_cpu(X) bswap32(X)
# define le16_to_cpu(X) (X)
# define le32_to_cpu(X) (X)
# define be16_to_cpu(X) bswap16(X)
# define be32_to_cpu(X) bswap32(X)
# define le16_to_cpu(X) (epicsUInt16)(X)
# define le32_to_cpu(X) (epicsUInt32)(X)
#else
# error Unable to determine native byte order
#endif
#if CPU_FAMILY == PPC
/* All PowerPC BSPs that I have studied implement these functions
* with the same definition, byte-swapping the data and adding a
* sync and/or eieio instruction as necessary on that CPU board.
* They do *not* all implement the sys{In/Out}{Byte/Word/Long}
* functions to do the same thing though, so we can't use them.
*/
UINT8 sysPciInByte(UINT8 *addr);
void sysPciOutByte(UINT8 *addr, UINT8 data);
UINT16 sysPciInWord(UINT16 *addr);
void sysPciOutWord(UINT16 *addr, UINT16 data);
UINT32 sysPciInLong (UINT32 *addr);
void sysPciOutLong (UINT32 *addr, UINT32 data);
#define ioread8(address) sysPciInByte((UINT8 *)(address))
#define iowrite8(address,data) sysPciOutByte((UINT8 *)(address), (epicsUInt8)(data))
#define nat_ioread16(address) bswap16(sysPciInWord((UINT16 *)(address)))
#define nat_ioread32(address) bswap32(sysPciInLong((UINT32 *)(address)))
#define nat_iowrite16(address,data) sysPciOutWord((UINT16 *)(address), bswap16(data))
#define nat_iowrite32(address,data) sysPciOutLong((UINT32 *)(address), bswap32(data))
#define be_ioread16(address) bswap16(sysPciInWord((UINT16 *)(address)))
#define be_ioread32(address) bswap32(sysPciInLong((UINT32 *)(address)))
#define be_iowrite16(address,data) sysPciOutWord((UINT16 *)(address), bswap16(data))
#define be_iowrite32(address,data) sysPciOutLong((UINT32 *)(address), bswap32(data))
#define le_ioread16(address) sysPciInWord((UINT16 *)(address))
#define le_ioread32(address) sysPciInLong((UINT32 *)(address))
#define le_iowrite16(address,data) sysPciOutWord((UINT16 *)(address), (data))
#define le_iowrite32(address,data) sysPciOutLong((UINT32 *)(address), (data))
#else /* CPU_FAMILY == I80X86 */
/* All Intel BSPs should implement the sys{In/Out}{Byte/Word/Long}
* functions, which are declared in the sysLib.h header.
*/
#define ioread8(address) sysInByte ((epicsUInt32)(address))
#define iowrite8(address,data) sysOutByte ((epicsUInt32)(address), (epicsUInt8)(data))
@@ -96,6 +139,9 @@
#define le_iowrite16(address,data) sysOutWord ((epicsUInt32)(address), le16_to_cpu((epicsUInt16)(data)))
#define le_iowrite32(address,data) sysOutLong ((epicsUInt32)(address), le32_to_cpu((epicsUInt32)(data)))
#endif /* I80X86 */
#ifndef VX_MEM_BARRIER_R
# define VX_MEM_BARRIER_R() do{}while(0)
#endif
@@ -110,5 +156,5 @@
#define wbarr() VX_MEM_BARRIER_W()
#define rwbarr() VX_MEM_BARRIER_RW()
#endif /* !MC680X0 */
#endif /* CPU_FAMILY */
#endif /* EPICSMMIO_H */