maliakal_d ce7f01bdc4 Dev: m3 clkdiv0 20 (#924) ...

* m3: clk 0 changed from 10 to 20 (100MHz to 50MHz)

* g2: startup clk div back to 10 as in firmware but setting in software startup to 20

* m3: minor print error if clk divider > max

2024-07-25 17:18:45 +02:00

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sls

Dev: m3 clkdiv0 20 (#924)

2024-07-25 17:18:45 +02:00