Dhanya Thattil ce7f01bdc4

Dev: m3 clkdiv0 20 (#924) ...

* m3: clk 0 changed from 10 to 20 (100MHz to 50MHz)

* g2: startup clk div back to 10 as in firmware but setting in software startup to 20

* m3: minor print error if clk divider > max

2024-07-25 17:18:45 +02:00

..

bin

Dev: m3 clkdiv0 20 (#924)

2024-07-25 17:18:45 +02:00

CMakeLists.txt

server side fixed

2021-11-08 17:24:51 +01:00

DefaultPattern_mythen3.txt

Pattern 6 levels (#493)

2022-07-14 12:00:07 +02:00

detid_mythen3.txt

moduleid made into dec not hex

2021-10-05 13:23:09 +02:00

Makefile

Versioning (#568)

2022-11-09 11:13:09 +01:00

mythen3.c

M3 deserialize (#618)

2023-01-17 09:39:58 +01:00

mythen3.h

M3badchannels (#526)

2022-09-01 15:30:04 +02:00

RegisterDefs.h

g2 and m3 round robin (#559)

2022-10-18 15:51:23 +02:00

slsDetectorFunctionList.c

Dev: m3 clkdiv0 20 (#924)

2024-07-25 17:18:45 +02:00

slsDetectorServer_defs.h

Dev: m3 clkdiv0 20 (#924)

2024-07-25 17:18:45 +02:00