Dhanya Thattil ce7f01bdc4

Dev: m3 clkdiv0 20 (#924) ...

* m3: clk 0 changed from 10 to 20 (100MHz to 50MHz)

* g2: startup clk div back to 10 as in firmware but setting in software startup to 20

* m3: minor print error if clk divider > max

2024-07-25 17:18:45 +02:00

..

ctbDetectorServer

updated binaries

2024-02-07 13:23:58 +01:00

eigerDetectorServer

Dev/xilinx acq (#901)

2024-02-07 13:23:08 +01:00

gotthard2DetectorServer

Dev/xilinx acq (#901)

2024-02-07 13:23:08 +01:00

gotthardDetectorServer

updated binaries

2024-02-07 13:23:58 +01:00

jungfrauDetectorServer

updated binaries

2024-02-07 13:23:58 +01:00

moenchDetectorServer

Dev: m3 clkdiv0 20 (#924)

2024-07-25 17:18:45 +02:00

mythen3DetectorServer

Dev: m3 clkdiv0 20 (#924)

2024-07-25 17:18:45 +02:00

slsDetectorServer

formatting

2024-02-07 13:25:11 +01:00

stripDetectorDaemon

make files

2021-10-18 11:52:23 +02:00

xilinx_ctbDetectorServer

formatting

2024-02-07 13:25:11 +01:00

CMakeLists.txt

Xilinx ctb (#884)

2024-01-04 17:10:16 +01:00

compileAllServers_noAPIUpdate.sh

Dev/xilinx defaults and pattern (#888)

2024-01-11 18:01:08 +01:00

compileAllServers.sh

Dev/xilinx defaults and pattern (#888)

2024-01-11 18:01:08 +01:00

compileEigerServer.sh

Versioning (#568)

2022-11-09 11:13:09 +01:00