Dhanya Thattil 969551ae37 program fpga made parallel

2019-03-29 17:59:06 +01:00

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ctbDetectorServer

ctb server: sync is min clock and must go higher when the others do

2019-03-28 14:22:40 +01:00

eigerDetectorServer

added eiger binary

2019-03-27 12:26:10 +01:00

gotthardDetectorServer

ctb & moench: phase fix for absolute within limits, option to set as degrees and get max phase shift, bug fix for eiger with implementation of 2 udp interface

2019-03-27 12:25:38 +01:00

jungfrauDetectorServer

program fpga made parallel

2019-03-29 17:59:06 +01:00

moenchDetectorServer

moench server: sync increases when other clocks do

2019-03-28 15:24:47 +01:00

slsDetectorServer

ctb server: pll reset to keep the phase after setting clock

2019-03-28 15:22:13 +01:00