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ctb & moench: phase fix for absolute within limits, option to set as degrees and get max phase shift, bug fix for eiger with implementation of 2 udp interface

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This commit is contained in:
maliakal_d 2019-03-27 12:25:38 +01:00
parent c7ad548e4c
commit c7c52c63cd
20 changed files with 667 additions and 454 deletions
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10
slsDetectorServers/ctbDetectorServer/gitInfo.txt
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@ -1,9 +1,9 @@
Path: slsDetectorPackage/slsDetectorServers/ctbDetectorServer
URL: origin git@github.com:slsdetectorgroup/slsDetectorPackage.git
Repository Root: origin git@github.com:slsdetectorgroup/slsDetectorPackage.git
Repsitory UUID: 7cd5bc8b2db6e89fbec4c06c65e683cf788338c0
Revision: 46
Branch: jungfrau
Repsitory UUID: c7ad548e4c2026a826b9f269f32d9970ce0a44e8
Revision: 48
Branch: refactor
Last Changed Author: Dhanya_Thattil
Last Changed Rev: 4474
Last Changed Date: 2019-03-26 15:01:04.000000002 +0100 ./slsDetectorServer_defs.h
Last Changed Rev: 4478
Last Changed Date: 2019-03-27 11:13:21.000000002 +0100 ../slsDetectorServer/slsDetectorServer_funcs.c

8
slsDetectorServers/ctbDetectorServer/gitInfoCtb.h
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@ -1,6 +1,6 @@
#define GITURL "git@github.com:slsdetectorgroup/slsDetectorPackage.git"
#define GITREPUUID "7cd5bc8b2db6e89fbec4c06c65e683cf788338c0"
#define GITREPUUID "c7ad548e4c2026a826b9f269f32d9970ce0a44e8"
#define GITAUTH "Dhanya_Thattil"
#define GITREV 0x4474
#define GITDATE 0x20190326
#define GITBRANCH "jungfrau"
#define GITREV 0x4478
#define GITDATE 0x20190327
#define GITBRANCH "refactor"

119
slsDetectorServers/ctbDetectorServer/slsDetectorFunctionList.c
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@ -781,16 +781,15 @@ ROI* setROI(int n, ROI arg[], int *retvalsize, int *ret) {
/* parameters - speed, readout */
void setSpeed(enum speedVariable ind, int val) {
void setSpeed(enum speedVariable ind, int val, int mode) {
switch(ind) {
case ADC_PHASE:
case PHASE_SHIFT:
FILE_LOG(logINFOBLUE, ("Configuring ADC Phase\n"));
configurePhase(ADC_CLK, val);
configurePhase(ADC_CLK, val, mode);
break;
case DBIT_PHASE:
FILE_LOG(logINFOBLUE, ("Configuring Dbit Phase\n"));
configurePhase(DBIT_CLK, val);
configurePhase(DBIT_CLK, val, mode);
break;
case ADC_CLOCK:
FILE_LOG(logINFOBLUE, ("Configuring ADC Clock\n"));
@ -818,23 +817,26 @@ void setSpeed(enum speedVariable ind, int val) {
}
}
int getSpeed(enum speedVariable ind) {
int getSpeed(enum speedVariable ind, int mode) {
switch(ind) {
case ADC_PHASE:
case PHASE_SHIFT:
return getPhase(ADC_CLK);
return getPhase(ADC_CLK, mode);
case DBIT_PHASE:
return getPhase(DBIT_CLK);
return getPhase(DBIT_CLK, mode);
case MAX_ADC_PHASE_SHIFT:
return getMaxPhase(ADC_CLK);
case MAX_DBIT_PHASE_SHIFT:
return getMaxPhase(DBIT_CLK);
case ADC_CLOCK:
return getFrequency(ADC_CLK);
case DBIT_CLOCK:
return getFrequency(DBIT_CLK);
case CLOCK_DIVIDER:
return getFrequency(RUN_CLK);
case ADC_PIPELINE:
return getAdcOffsetRegister(1);
case DBIT_PIPELINE:
return getAdcOffsetRegister(0);
case CLOCK_DIVIDER:
return getFrequency(RUN_CLK);
default:
return -1;
}
@ -1633,41 +1635,100 @@ int enableTenGigabitEthernet(int val) {
// ind can only be ADC_CLK or DBIT_CLK
void configurePhase(enum CLKINDEX ind, int val) {
char clock_names[4][10]={"run_clk","adc_clk", "sync_clk", "dbit_clk"};
if (val > 65535 || val < -65535) {
FILE_LOG(logERROR, ("\tPhase provided for C%d(%s) outside limits\n", ind, clock_names[ind]));
return;
}
int relativePhase = clkPhase[ind] - val;
void configurePhase(enum CLKINDEX ind, int val, int degrees) {
char clock_names[4][10]={"run_clk","adc_clk", "sync_clk", "dbit_clk"};
int maxShift = getMaxPhase(ind);
// validation
if (degrees && (val < 0 || val > 359)) {
FILE_LOG(logERROR, ("\tPhase provided for C%d(%s) outside limits (0 - 359°C)\n", ind, clock_names[ind]));
return;
}
if (!degrees && (val < 0 || val > maxShift - 1)) {
FILE_LOG(logERROR, ("\tPhase provided for C%d(%s) outside limits (0 - %d phase shifts)\n", ind, clock_names[ind], maxShift - 1));
return;
}
FILE_LOG(logINFO, ("Configuring Phase of C%d(%s) to %d (degree mode: %d)\n", ind, clock_names[ind], val, degrees));
int valShift = val;
// convert to phase shift
if (degrees) {
double temp = val * ((double)maxShift / 360.00);
if ((temp - (int)temp) > 0.0001) {
temp += 0.5;
}
valShift = temp;
FILE_LOG(logDEBUG1, ("phase shift: %d\n", valShift));
}
FILE_LOG(logDEBUG1, ("phase shift: %d (degrees/shift: %d)\n", valShift, val));
int relativePhase = clkPhase[ind] - valShift;
FILE_LOG(logDEBUG1, ("relative phase shift: %d (Current phase: %d)\n", relativePhase, clkPhase[ind]));
// same phase
if (!relativePhase) {
FILE_LOG(logDEBUG1, ("Nothing to do\n"));
return;
}
FILE_LOG(logINFO, ("Configuring Phase of C%d(%s) to %d\n", ind, clock_names[ind], val));
int phase = 0;
int maxShifts = (PLL_VCO_FREQ_MHZ / clkDivider[ind]) * MAX_PHASE_SHIFTS_STEPS;
FILE_LOG(logDEBUG1, ("Clock: %d MHz, VCO:%d MHz, Max Phase shifts:%d\n",
clkDivider[ind], PLL_VCO_FREQ_MHZ, maxShifts));
// delay clk
if (relativePhase > 0) {
phase = (maxShifts - relativePhase);
phase = (maxShift - relativePhase);
} else {
phase = (-1) * relativePhase;
}
FILE_LOG(logINFO, ("\tphase out %d (0x%08x)\n", phase, phase));
FILE_LOG(logDEBUG1, ("[Single Direction] Phase:%d (0x%x). Max Phase shifts:%d\n", phase, phase, maxShift));
ALTERA_PLL_SetPhaseShift(phase, (int)ind, 0);
clkPhase[ind] = val;
clkPhase[ind] = valShift;
}
int getPhase(enum CLKINDEX ind) {
return clkPhase[ind];
int getPhase(enum CLKINDEX ind, int degrees) {
if (!degrees)
return clkPhase[ind];
return (clkPhase[ind] * (360.00 / (double)getMaxPhase(ind)));
}
int getMaxPhase(enum CLKINDEX ind) {
int ret = ((double)PLL_VCO_FREQ_MHZ / (double)clkDivider[ind]) * MAX_PHASE_SHIFTS_STEPS;
char clock_names[4][10]={"run_clk","adc_clk", "sync_clk", "dbit_clk"};
FILE_LOG(logDEBUG1, ("Max Phase Shift (%s): %d (Clock: %d MHz, VCO:%d MHz)\n",
clock_names[ind], ret, clkDivider[ind], PLL_VCO_FREQ_MHZ));
return ret;
}
int validatePhaseinDegrees(enum speedVariable ind, int val, int retval) {
if (val == -1)
return OK;
enum CLKINDEX clkIndex;
switch(ind) {
case ADC_PHASE:
clkIndex = ADC_CLK;
break;
case DBIT_PHASE:
clkIndex = DBIT_CLK;
break;
default:
FILE_LOG(logERROR, ("Unknown speed enum %d for validating phase in degrees\n", (int)ind));
}
FILE_LOG(logDEBUG1, ("validating phase in degrees for clk %d\n", clkIndex));
int maxShift = getMaxPhase(clkIndex);
// convert degrees to shift
double temp = val;
temp *= ((double)maxShift / 360.00);
if ((temp - (int)temp) > 0.0001) {
temp += 0.5;
}
val = (int)temp;
// convert back to degrees
val *= (360.00 / (double)maxShift);
if (val == retval)
return OK;
return FAIL;
}
void configureFrequency(enum CLKINDEX ind, int val) {

17
slsDetectorServers/eigerDetectorServer/Beb.c
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@ -1209,16 +1209,19 @@ int Beb_SetDetectorPosition(int pos[]) {
value &= UDP_HEADER_ID_MSK; // to keep previous id value
Beb_Write32(csp0base, UDP_HEADER_A_LEFT_OFST, value | ((pos[0] << UDP_HEADER_X_OFST) & UDP_HEADER_X_MSK));
value = Beb_Read32(csp0base, UDP_HEADER_A_LEFT_OFST);
if ((value & UDP_HEADER_X_MSK) != ((pos[0] << UDP_HEADER_X_OFST) & UDP_HEADER_X_MSK))
if ((value & UDP_HEADER_X_MSK) != ((pos[0] << UDP_HEADER_X_OFST) & UDP_HEADER_X_MSK)) {
FILE_LOG(logERROR, ("Could not set row position for left port\n"));
ret = FAIL;
}
// x right
value = Beb_Read32(csp0base, UDP_HEADER_A_RIGHT_OFST);
value &= UDP_HEADER_ID_MSK; // to keep previous id value
Beb_Write32(csp0base, UDP_HEADER_A_RIGHT_OFST, value | ((pos[0] << UDP_HEADER_X_OFST) & UDP_HEADER_X_MSK));
value = Beb_Read32(csp0base, UDP_HEADER_A_RIGHT_OFST);
if ((value & UDP_HEADER_X_MSK) != ((pos[0] << UDP_HEADER_X_OFST) & UDP_HEADER_X_MSK))
if ((value & UDP_HEADER_X_MSK) != ((pos[0] << UDP_HEADER_X_OFST) & UDP_HEADER_X_MSK)) {
FILE_LOG(logERROR, ("Could not set row position for right port\n"));
ret = FAIL;
}
@ -1228,8 +1231,10 @@ int Beb_SetDetectorPosition(int pos[]) {
value &= UDP_HEADER_Z_MSK; // to keep previous z value
Beb_Write32(csp0base, UDP_HEADER_B_LEFT_OFST, value | ((posval << UDP_HEADER_Y_OFST) & UDP_HEADER_Y_MSK));
value = Beb_Read32(csp0base, UDP_HEADER_B_LEFT_OFST);
if ((value & UDP_HEADER_Z_MSK) != ((posval << UDP_HEADER_Y_OFST) & UDP_HEADER_Y_MSK))
if ((value & UDP_HEADER_Y_MSK) != ((posval << UDP_HEADER_Y_OFST) & UDP_HEADER_Y_MSK)) {
FILE_LOG(logERROR, ("Could not set column position for left port\n"));
ret = FAIL;
}
// y right
value = Beb_Read32(csp0base, UDP_HEADER_B_RIGHT_OFST);
@ -1237,8 +1242,10 @@ int Beb_SetDetectorPosition(int pos[]) {
posval = Beb_swap_uint16(Beb_top ? (pos[1]+1) : pos[1]);
Beb_Write32(csp0base, UDP_HEADER_B_RIGHT_OFST, value | ((posval << UDP_HEADER_Y_OFST) & UDP_HEADER_Y_MSK));
value = Beb_Read32(csp0base, UDP_HEADER_B_RIGHT_OFST);
if ((value & UDP_HEADER_Z_MSK) != ((posval << UDP_HEADER_Y_OFST) & UDP_HEADER_Y_MSK))
if ((value & UDP_HEADER_Y_MSK) != ((posval << UDP_HEADER_Y_OFST) & UDP_HEADER_Y_MSK)) {
FILE_LOG(logERROR, ("Could not set column position for right port\n"));
ret = FAIL;
}
//close file pointer

10
slsDetectorServers/eigerDetectorServer/gitInfo.txt
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@ -1,9 +1,9 @@
Path: slsDetectorPackage/slsDetectorServers/eigerDetectorServer
URL: origin git@github.com:slsdetectorgroup/slsDetectorPackage.git
Repository Root: origin git@github.com:slsdetectorgroup/slsDetectorPackage.git
Repsitory UUID: cd5aea895b07b7af25e3fb74a341a861f9aa291c
Revision: 30
Branch: jungfrau
Repsitory UUID: c7ad548e4c2026a826b9f269f32d9970ce0a44e8
Revision: 31
Branch: refactor
Last Changed Author: Dhanya_Thattil
Last Changed Rev: 4473
Last Changed Date: 2019-03-22 17:13:44.000000002 +0100 ../slsDetectorServer/slsDetectorServer_funcs.c
Last Changed Rev: 4478
Last Changed Date: 2019-03-27 08:46:12.000000002 +0100 ./Beb.c

8
slsDetectorServers/eigerDetectorServer/gitInfoEiger.h
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@ -1,6 +1,6 @@
#define GITURL "git@github.com:slsdetectorgroup/slsDetectorPackage.git"
#define GITREPUUID "cd5aea895b07b7af25e3fb74a341a861f9aa291c"
#define GITREPUUID "c7ad548e4c2026a826b9f269f32d9970ce0a44e8"
#define GITAUTH "Dhanya_Thattil"
#define GITREV 0x4473
#define GITDATE 0x20190322
#define GITBRANCH "jungfrau"
#define GITREV 0x4478
#define GITDATE 0x20190327
#define GITBRANCH "refactor"

15
slsDetectorServers/gotthardDetectorServer/slsDetectorFunctionList.c
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@ -820,6 +820,21 @@ ROI* setROI(int n, ROI arg[], int *retvalsize, int *ret) {
return rois;
}
// parameters - readout
void setSpeed(enum speedVariable ind, int val) {
switch(ind) {
case ADC_PHASE:
setPhaseShift(val);
break;
default:
return;
}
}
int getSpeed(enum speedVariable ind) {
// cannot get phase shift
return -1;
}
/* parameters - timer */

11
slsDetectorServers/moenchDetectorServer/RegisterDefs.h
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@ -533,17 +533,6 @@
#define PATTERN_SET_LSB_REG (0x82 << MEM_MAP_SHIFT)
#define PATTERN_SET_MSB_REG (0x83 << MEM_MAP_SHIFT)
/** I2C Control register */
//#define I2C_TRANSFER_COMMAND_FIFO_REG (0x100 << MEM_MAP_SHIFT) // in FW, but not used anywhere
//#define I2C_CONTROL_REG (0x102 << MEM_MAP_SHIFT) // in FW, but not used anywhere
//#define I2C_RX_DATA_FIFO_LEVEL_REG (0x107 << MEM_MAP_SHIFT) // in FW, but not used anywhere
//#define I2C_SCL_LOW_COUNT_REG (0x108 << MEM_MAP_SHIFT) // in FW, but not used anywhere
//#define I2C_SCL_HIGH_COUNT_REG (0x109 << MEM_MAP_SHIFT) // in FW, but not used anywhere
//#define I2C_SDA_HOLD_REG (0x10A << MEM_MAP_SHIFT) // in FW, but not used anywhere

178
slsDetectorServers/moenchDetectorServer/slsDetectorFunctionList.c
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@ -757,16 +757,15 @@ ROI* setROI(int n, ROI arg[], int *retvalsize, int *ret) {
/* parameters - speed, readout */
void setSpeed(enum speedVariable ind, int val) {
void setSpeed(enum speedVariable ind, int val, int mode) {
switch(ind) {
case ADC_PHASE:
case PHASE_SHIFT:
FILE_LOG(logINFOBLUE, ("Configuring ADC Phase\n"));
configurePhase(ADC_CLK, val);
configurePhase(ADC_CLK, val, mode);
break;
case DBIT_PHASE:
FILE_LOG(logINFOBLUE, ("Configuring Dbit Phase\n"));
configurePhase(DBIT_CLK, val);
configurePhase(DBIT_CLK, val, mode);
break;
case ADC_CLOCK:
FILE_LOG(logINFOBLUE, ("Configuring ADC Clock\n"));
@ -794,23 +793,26 @@ void setSpeed(enum speedVariable ind, int val) {
}
}
int getSpeed(enum speedVariable ind) {
int getSpeed(enum speedVariable ind, int mode) {
switch(ind) {
case ADC_PHASE:
case PHASE_SHIFT:
return getPhase(ADC_CLK);
return getPhase(ADC_CLK, mode);
case DBIT_PHASE:
return getPhase(DBIT_CLK);
return getPhase(DBIT_CLK, mode);
case MAX_ADC_PHASE_SHIFT:
return getMaxPhase(ADC_CLK);
case MAX_DBIT_PHASE_SHIFT:
return getMaxPhase(DBIT_CLK);
case ADC_CLOCK:
return getFrequency(ADC_CLK);
case DBIT_CLOCK:
return getFrequency(DBIT_CLK);
case CLOCK_DIVIDER:
return getFrequency(RUN_CLK);
case ADC_PIPELINE:
return getAdcOffsetRegister(1);
case DBIT_PIPELINE:
return getAdcOffsetRegister(0);
case CLOCK_DIVIDER:
return getFrequency(RUN_CLK);
default:
return -1;
}
@ -1269,48 +1271,100 @@ int powerChip(int on) {
}
// ind can only be ADC_CLK or DBIT_CLK
void configurePhase(enum CLKINDEX ind, int val) {
char clock_names[4][10]={"run_clk","adc_clk", "sync_clk", "dbit_clk"};
if (val > 65535 || val < -65535) {
FILE_LOG(logERROR, ("\tPhase provided for C%d(%s) outside limits\n", ind, clock_names[ind]));
return;
}
int relativePhase = clkPhase[ind] - val;
void configurePhase(enum CLKINDEX ind, int val, int degrees) {
char clock_names[4][10]={"run_clk","adc_clk", "sync_clk", "dbit_clk"};
int maxShift = getMaxPhase(ind);
// validation
if (degrees && (val < 0 || val > 359)) {
FILE_LOG(logERROR, ("\tPhase provided for C%d(%s) outside limits (0 - 359°C)\n", ind, clock_names[ind]));
return;
}
if (!degrees && (val < 0 || val > maxShift - 1)) {
FILE_LOG(logERROR, ("\tPhase provided for C%d(%s) outside limits (0 - %d phase shifts)\n", ind, clock_names[ind], maxShift - 1));
return;
}
FILE_LOG(logINFO, ("Configuring Phase of C%d(%s) to %d (degree mode: %d)\n", ind, clock_names[ind], val, degrees));
int valShift = val;
// convert to phase shift
if (degrees) {
double temp = val * ((double)maxShift / 360.00);
if ((temp - (int)temp) > 0.0001) {
temp += 0.5;
}
valShift = temp;
FILE_LOG(logDEBUG1, ("phase shift: %d\n", valShift));
}
FILE_LOG(logDEBUG1, ("phase shift: %d (degrees/shift: %d)\n", valShift, val));
int relativePhase = clkPhase[ind] - valShift;
FILE_LOG(logDEBUG1, ("relative phase shift: %d (Current phase: %d)\n", relativePhase, clkPhase[ind]));
// same phase
if (!relativePhase) {
FILE_LOG(logDEBUG1, ("Nothing to do\n"));
return;
}
FILE_LOG(logINFO, ("Configuring Phase of C%d(%s) to %d\n", ind, clock_names[ind], val));
// reset only pll
ALTERA_PLL_ResetPLL();
// set mode register to polling mode
ALTERA_PLL_SetModePolling();
int phase = 0;
int maxShifts = (PLL_VCO_FREQ_MHZ / clkDivider[ind]) * MAX_PHASE_SHIFTS_STEPS;
FILE_LOG(logDEBUG1, ("Clock: %d MHz, VCO:%d MHz, Max Phase shifts:%d\n",
clkDivider[ind], PLL_VCO_FREQ_MHZ, maxShifts));
// delay clk
if (relativePhase > 0) {
phase = (maxShifts - relativePhase);
phase = (maxShift - relativePhase);
} else {
phase = (-1) * relativePhase;
}
FILE_LOG(logINFO, ("\tphase out %d (0x%08x)\n", phase, phase));
FILE_LOG(logDEBUG1, ("[Single Direction] Phase:%d (0x%x). Max Phase shifts:%d\n", phase, phase, maxShift));
ALTERA_PLL_SetPhaseShift(phase, (int)ind, 0);
clkPhase[ind] = val;
clkPhase[ind] = valShift;
}
int getPhase(enum CLKINDEX ind) {
return clkPhase[ind];
int getPhase(enum CLKINDEX ind, int degrees) {
if (!degrees)
return clkPhase[ind];
return (clkPhase[ind] * (360.00 / (double)getMaxPhase(ind)));
}
int getMaxPhase(enum CLKINDEX ind) {
int ret = ((double)PLL_VCO_FREQ_MHZ / (double)clkDivider[ind]) * MAX_PHASE_SHIFTS_STEPS;
char clock_names[4][10]={"run_clk","adc_clk", "sync_clk", "dbit_clk"};
FILE_LOG(logDEBUG1, ("Max Phase Shift (%s): %d (Clock: %d MHz, VCO:%d MHz)\n",
clock_names[ind], ret, clkDivider[ind], PLL_VCO_FREQ_MHZ));
return ret;
}
int validatePhaseinDegrees(enum speedVariable ind, int val, int retval) {
if (val == -1)
return OK;
enum CLKINDEX clkIndex;
switch(ind) {
case ADC_PHASE:
clkIndex = ADC_CLK;
break;
case DBIT_PHASE:
clkIndex = DBIT_CLK;
break;
default:
FILE_LOG(logERROR, ("Unknown speed enum %d for validating phase in degrees\n", (int)ind));
}
FILE_LOG(logDEBUG1, ("validating phase in degrees for clk %d\n", clkIndex));
int maxShift = getMaxPhase(clkIndex);
// convert degrees to shift
double temp = val;
temp *= ((double)maxShift / 360.00);
if ((temp - (int)temp) > 0.0001) {
temp += 0.5;
}
val = (int)temp;
// convert back to degrees
val *= (360.00 / (double)maxShift);
if (val == retval)
return OK;
return FAIL;
}
void configureFrequency(enum CLKINDEX ind, int val) {
@ -1929,23 +1983,45 @@ void unsetFifoReadStrobes() {
void readSample(int ns) {
uint32_t addr = DUMMY_REG;
// read analog data
uint32_t fifoAddr = FIFO_DATA_REG;
// read digital output
// read strobe to digital fifo
bus_w(addr, bus_r(addr) | DUMMY_DGTL_FIFO_RD_STRBE_MSK);
bus_w(addr, bus_r(addr) & (~DUMMY_DGTL_FIFO_RD_STRBE_MSK));
// wait as it is connected directly to fifo running on a different clock
if (!(ns%1000)) {
FILE_LOG(logDEBUG1, ("Reading sample ns:%d of %d DEmtpy:%d DFull:%d Status:0x%x\n",
ns, nSamples,
((bus_r(FIFO_DIN_STATUS_REG) & FIFO_DIN_STATUS_FIFO_EMPTY_MSK) >> FIFO_DIN_STATUS_FIFO_EMPTY_OFST),
((bus_r(FIFO_DIN_STATUS_REG) & FIFO_DIN_STATUS_FIFO_FULL_MSK) >> FIFO_DIN_STATUS_FIFO_FULL_OFST),
bus_r(STATUS_REG)));
}
// read strobe to all analog fifos
bus_w(addr, bus_r(addr) | DUMMY_ANLG_FIFO_RD_STRBE_MSK);
bus_w(addr, bus_r(addr) & (~DUMMY_ANLG_FIFO_RD_STRBE_MSK));
// wait as it is connected directly to fifo running on a different clock
//usleep(WAIT_TIME_FIFO_RD_STROBE);
if (!(ns%1000)) {
FILE_LOG(logDEBUG1, ("Reading sample ns:%d of %d AEmtpy:0x%x AFull:0x%x Status:0x%x\n",
ns, nSamples, bus_r(FIFO_EMPTY_REG), bus_r(FIFO_FULL_REG), bus_r(STATUS_REG)));
}
// read fifo and write it to current position of data pointer
*((uint64_t*)now_ptr) = get64BitReg(FIFO_DIN_LSB_REG, FIFO_DIN_MSB_REG);
now_ptr += 8;
// loop through all channels
int ich = 0;
for (ich = 0; ich < NCHAN_ANALOG; ++ich) {
// if channel is in ROI
if ((1 << ich) & ~(adcDisableMask)) {
// unselect channel
bus_w(addr, bus_r(addr) & ~(DUMMY_FIFO_CHNNL_SLCT_MSK));
// select channel
bus_w(addr, bus_r(addr) | ((ich << DUMMY_FIFO_CHNNL_SLCT_OFST) & DUMMY_FIFO_CHNNL_SLCT_MSK));
// read fifo and write it to current position of data pointer
*((uint16_t*)now_ptr) = bus_r16(fifoAddr);
// keep reading till the value is the same
/* while (*((uint16_t*)now_ptr) != bus_r16(fifoAddr)) {
FILE_LOG(logDEBUG1, ("%d ", ich));
*((uint16_t*)now_ptr) = bus_r16(fifoAddr);
}*/
// increment pointer to data out destination
now_ptr += 2;
}
}
}

2
slsDetectorServers/slsDetectorServer/ALTERA_PLL.h
View File

@ -207,7 +207,7 @@ int ALTERA_PLL_SetOuputFrequency (int clkIndex, int pllVCOFreqMhz, int value) {
uint32_t low_count = total_div / 2;
uint32_t high_count = low_count;
uint32_t odd_division = 0;
cprintf(RED, "toatldiv:%f\n", total_div);
// odd division
if (total_div > (float)(2 * low_count)) {
++high_count;

11
slsDetectorServers/slsDetectorServer/slsDetectorFunctionList.h
View File

@ -115,7 +115,10 @@ ROI* setROI(int n, ROI arg[], int *retvalsize, int *ret);
#endif
// parameters - readout
#ifndef GOTTHARDD
#if defined(CHIPTESTBOARDD) || defined(MOENCHD)
void setSpeed(enum speedVariable ind, int val, int mode);
int getSpeed(enum speedVariable ind, int mode);
#else
void setSpeed(enum speedVariable ind, int val);
int getSpeed(enum speedVariable ind);
#endif
@ -238,8 +241,10 @@ int powerChip (int on);
// chip test board or moench specific - configure frequency, phase, pll, flashing firmware
#if defined(CHIPTESTBOARDD) || defined(MOENCHD)
void configurePhase(enum CLKINDEX ind, int val);
int getPhase(enum CLKINDEX ind);
void configurePhase(enum CLKINDEX ind, int val, int degrees);
int getPhase(enum CLKINDEX ind, int degrees);
int getMaxPhase(enum CLKINDEX ind);
int validatePhaseinDegrees(enum speedVariable ind, int val, int retval);
void configureFrequency(enum CLKINDEX ind, int val);
int getFrequency(enum CLKINDEX ind);
void configureSyncFrequency(enum CLKINDEX ind);

88
slsDetectorServers/slsDetectorServer/slsDetectorServer_funcs.c
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@ -140,14 +140,14 @@ const char* getTimerName(enum timerIndex ind) {
const char* getSpeedName(enum speedVariable ind) {
switch (ind) {
case CLOCK_DIVIDER: return "clock_divider";
case PHASE_SHIFT: return "phase_shift";
case OVERSAMPLING: return "oversampling";
case ADC_CLOCK: return "adc_clock";
case ADC_PHASE: return "adc_phase";
case ADC_PIPELINE: return "adc_pipeline";
case DBIT_CLOCK: return "dbit_clock";
case DBIT_PHASE: return "dbit_phase";
case DBIT_PIPELINE: return "dbit_pipeline";
case MAX_ADC_PHASE_SHIFT: return "max_adc_phase_shift";
case MAX_DBIT_PHASE_SHIFT: return "max_dbit_phase_shift";
default: return "unknown_speed";
}
}
@ -1938,74 +1938,98 @@ int set_roi(int file_des) {
int set_speed(int file_des) {
ret = OK;
memset(mess, 0, sizeof(mess));
int args[2] = {-1,-1};
int args[3] = {-1, -1, -1};
int retval = -1;
if (receiveData(file_des, args, sizeof(args), INT32) < 0)
return printSocketReadError();
#ifdef GOTTHARDD
functionNotImplemented();
#else
enum speedVariable ind = args[0];
int val = args[1];
int GET_VAL = -1;
if ((ind == PHASE_SHIFT) || (ind == ADC_PHASE) || (ind == DBIT_PHASE))
GET_VAL = 100000;
int mode = args[2];
char speedName[20] = {0};
strcpy(speedName, getSpeedName(ind));
FILE_LOG(logDEBUG1, ("Setting speed index %s (%d) to %d\n", speedName, ind, val));
FILE_LOG(logDEBUG1, ("Setting speed index %s (speedVariable %d) to %d (mode: %d)\n", speedName, ind, val, mode));
// check index
switch(ind) {
#ifdef JUNGFRAUD
case ADC_PHASE:
case CLOCK_DIVIDER:
#elif CHIPTESTBOARDD
case ADC_PHASE:
case PHASE_SHIFT:
case DBIT_PHASE:
case MAX_ADC_PHASE_SHIFT:
case MAX_DBIT_PHASE_SHIFT:
case ADC_CLOCK:
case DBIT_CLOCK:
case CLOCK_DIVIDER:
case ADC_PIPELINE:
case DBIT_PIPELINE:
#elif MOENCHD
case ADC_PHASE:
case PHASE_SHIFT:
case DBIT_PHASE:
case MAX_ADC_PHASE_SHIFT:
case MAX_DBIT_PHASE_SHIFT:
case ADC_CLOCK:
case DBIT_CLOCK:
case CLOCK_DIVIDER:
case ADC_PIPELINE:
case DBIT_PIPELINE:
#endif
#elif GOTTHARDD
case ADC_PHASE:
#elif EIGERD
case CLOCK_DIVIDER:
#endif
break;
default:
modeNotImplemented(speedName, (int)ind);
break;
}
if (ret == OK) {
// set
if ((val != GET_VAL) && (Server_VerifyLock() == OK)) {
setSpeed(ind, val);
}
// get
retval = getSpeed(ind);
FILE_LOG(logDEBUG1, ("%s: %d\n", speedName, retval));
// validate
if (GET_VAL == -1) {
char validateName[20] = {0};
sprintf(validateName, "set %s", speedName);
validate(val, retval, validateName, DEC);
} else if (ret == OK && val != GET_VAL && retval != val ) {
ret = FAIL;
sprintf(mess, "Could not set %s. Set %d, but read %d\n", speedName, val, retval);
FILE_LOG(logERROR,(mess));
}
#if (!defined(CHIPTESTBOARDD)) && (!defined(MOENCHD))
if (ret == OK && mode == 1) {
ret = FAIL;
strcpy(mess, "deg is not defined for this detector.\n");
FILE_LOG(logERROR,(mess));
}
#endif
if (ret == OK) {
// set
if ((val != -1) && (Server_VerifyLock() == OK)) {
#if defined(CHIPTESTBOARDD) || defined(MOENCHD)
setSpeed(ind, val, mode);
#else
setSpeed(ind, val);
#endif
}
// get
#if defined(CHIPTESTBOARDD) || defined(MOENCHD)
retval = getSpeed(ind, mode);
#else
retval = getSpeed(ind);
#endif
FILE_LOG(logDEBUG1, ("%s: %d (mode:%d)\n", speedName, retval, mode));
// validate
char validateName[20] = {0};
sprintf(validateName, "set %s", speedName);
#ifndef GOTTHARDD
#if defined(CHIPTESTBOARDD) || defined(MOENCHD)
if (ind == ADC_PHASE || ind == DBIT_PHASE && mode == 1) {
ret = validatePhaseinDegrees(ind, val, retval);
if (ret == FAIL) {
sprintf(mess, "Could not set %s. Set %s, got %s\n", validateName);
FILE_LOG(logERROR,(mess));
}
} else
validate(val, retval, validateName, DEC);
#else
validate(val, retval, validateName, DEC);
#endif
#endif
}
return Server_SendResult(file_des, INT32, UPDATE, &retval, sizeof(retval));
}

6
slsDetectorSoftware/include/multiSlsDetector.h
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@ -734,14 +734,14 @@ class multiSlsDetector : public virtual slsDetectorDefs {
/**
* Set speed
* @param sp speed type (clkdivider option for Jungfrau and Eiger, others
* for Mythen/Gotthard)
* @param sp speed type (clkdivider option for Jungfrau and Eiger,
* adcphase for Gotthard, others for CTB & Moench)
* @param value (clkdivider 0,1,2 for full, half and quarter speed). Other
* values check manual
* @param detPos -1 for all detectors in list or specific detector position
* @returns value of speed set
*/
int setSpeed(speedVariable index, int value = -1, int detPos = -1);
int setSpeed(speedVariable index, int value = -1, int mode = 0, int detPos = -1);
/**
* Set/get dynamic range and updates the number of dataBytes

5
slsDetectorSoftware/include/slsDetector.h
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@ -697,11 +697,12 @@ class slsDetector : public virtual slsDetectorDefs{
/**
* Set speed
* @param sp speed type (clkdivider option for Jungfrau and Eiger, others for Mythen/Gotthard)
* @param sp speed type (clkdivider option for Jungfrau and Eiger,
* adcphase for Gotthard, others for CTB & Moench)
* @param value (clkdivider 0,1,2 for full, half and quarter speed). Other values check manual
* @returns value of speed set
*/
int setSpeed(speedVariable sp, int value = -1);
int setSpeed(speedVariable sp, int value = -1, int mode = 0);
/**
* Set/get dynamic range and updates the number of dataBytes

6
slsDetectorSoftware/src/multiSlsDetector.cpp
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@ -1199,14 +1199,14 @@ int64_t multiSlsDetector::getTimeLeft(timerIndex index, int detPos) {
return sls::minusOneIfDifferent(r);
}
int multiSlsDetector::setSpeed(speedVariable index, int value, int detPos) {
int multiSlsDetector::setSpeed(speedVariable index, int value, int mode, int detPos) {
// single
if (detPos >= 0) {
return detectors[detPos]->setSpeed(index, value);
return detectors[detPos]->setSpeed(index, value, mode);
}
// multi
auto r = parallelCall(&slsDetector::setSpeed, index, value);
auto r = parallelCall(&slsDetector::setSpeed, index, value, mode);
return sls::minusOneIfDifferent(r);
}

6
slsDetectorSoftware/src/slsDetector.cpp
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@ -1840,12 +1840,12 @@ int64_t slsDetector::getTimeLeft(timerIndex index) {
return retval;
}
int slsDetector::setSpeed(speedVariable sp, int value) {
int slsDetector::setSpeed(speedVariable sp, int value, int mode) {
int fnum = F_SET_SPEED;
int ret = FAIL;
int args[2] = {(int)sp, value};
int args[3] = {(int)sp, value, mode};
int retval = -1;
FILE_LOG(logDEBUG1) << "Setting speed index " << sp << " to " << value;
FILE_LOG(logDEBUG1) << "Setting speed index " << sp << " to " << value << " mode: " << mode;
if (detector_shm()->onlineFlag == ONLINE_FLAG) {
auto client = DetectorSocket(detector_shm()->hostname, detector_shm()->controlPort);

600
slsDetectorSoftware/src/slsDetectorCommand.cpp
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File diff suppressed because it is too large Load Diff

4
slsReceiverSoftware/src/slsReceiverImplementation.cpp
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@ -722,8 +722,10 @@ int slsReceiverImplementation::setUDPSocketBufferSize(const int64_t s) {
int64_t size = (s == 0) ? udpSocketBufferSize : s;
size_t listSize = listener.size();
if ((int)listSize != numUDPInterfaces)
if (myDetectorType == JUNGFRAU && (int)listSize != numUDPInterfaces) {
FILE_LOG(logERROR) << "Number of Interfaces " << numUDPInterfaces << " do not match listener size " << listSize;
return FAIL;
}
for (unsigned int i = 0; i < listSize; ++i) {
if (listener[i]->CreateDummySocketForUDPSocketBufferSize(size) == FAIL)

11
slsReceiverSoftware/src/slsReceiverTCPIPInterface.cpp
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@ -733,13 +733,16 @@ int slsReceiverTCPIPInterface::setup_udp(){
uint32_t port2 = atoi(args[5]);
// using the 2nd interface only
if (numInterfaces == 1 && selInterface == 2) {
if (myDetectorType == JUNGFRAU && numInterfaces == 1 && selInterface == 2) {
ip1 = ip2;
port1 = port2;
}
// 1st interface
receiver->setUDPPortNumber(port1);
if (myDetectorType == EIGER) {
receiver->setUDPPortNumber2(port2);
}
FILE_LOG(logINFO) << "Receiver UDP IP: " << ip1;
// get eth
std::string temp = genericSocket::ipToName(ip1);
@ -769,7 +772,7 @@ int slsReceiverTCPIPInterface::setup_udp(){
FILE_LOG(logERROR) << mess;
} else {
// using the 2nd interface only
if (numInterfaces == 1 && selInterface == 2) {
if (myDetectorType == JUNGFRAU && numInterfaces == 1 && selInterface == 2) {
strcpy(retvals[1],temp.c_str());
FILE_LOG(logINFO) << "Receiver MAC Address: " << retvals[1];
}
@ -782,7 +785,7 @@ int slsReceiverTCPIPInterface::setup_udp(){
}
// 2nd interface
if (numInterfaces == 2) {
if (myDetectorType == JUNGFRAU && numInterfaces == 2) {
receiver->setUDPPortNumber2(port2);
FILE_LOG(logINFO) << "Receiver UDP IP 2: " << ip2;
// get eth
@ -820,7 +823,7 @@ int slsReceiverTCPIPInterface::setup_udp(){
}
// set the number of udp interfaces (changes number of threads and many others)
if (receiver->setNumberofUDPInterfaces(numInterfaces) == FAIL) {
if (myDetectorType == JUNGFRAU && receiver->setNumberofUDPInterfaces(numInterfaces) == FAIL) {
ret = FAIL;
sprintf(mess, "Failed to set number of interfaces\n");
FILE_LOG(logERROR) << mess;

6
slsSupportLib/include/sls_detector_defs.h
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@ -502,14 +502,14 @@ public:
*/
enum speedVariable {
CLOCK_DIVIDER, /**< readout clock divider */
PHASE_SHIFT, /**< adds phase shift */
OVERSAMPLING, /**< oversampling for analog detectors */
ADC_CLOCK, /**< adc clock divider */
ADC_PHASE, /**< adc clock phase */
ADC_PIPELINE, /**< adc pipeline */
DBIT_CLOCK, /**< adc clock divider */
DBIT_PHASE, /**< adc clock phase */
DBIT_PIPELINE /**< adc pipeline */
DBIT_PIPELINE, /**< adc pipeline */
MAX_ADC_PHASE_SHIFT, /** max adc phase shift */
MAX_DBIT_PHASE_SHIFT, /** max adc phase shift */
};