Dhanya Thattil 8ada7b6e37
802: jungfrau HW 1.0: adc output clock phase to 120 (#951)
* jungfrau: change adc output clock phase from 180 to 120 for v1.0 boards for reliable readout of adc #2

* formatting
2024-08-22 14:27:16 +02:00

14 lines
500 B
C

// SPDX-License-Identifier: LGPL-3.0-or-other
// Copyright (C) 2021 Contributors to the SLS Detector Package
/** API versions */
#define RELEASE "8.0.1"
#define APIRECEIVER "8.0.0 0x231108"
#define APICTB "8.0.0 0x231109"
#define APIGOTTHARD "8.0.0 0x231109"
#define APIGOTTHARD2 "8.0.0 0x231109"
#define APIEIGER "8.0.0 0x231109"
#define APILIB "8.0.1 0x240112"
#define APIMOENCH "8.0.2 0x240703"
#define APIMYTHEN3 "8.0.2 0x240715"
#define APIJUNGFRAU "8.0.2 0x240822"