Dhanya Thattil 8ada7b6e37

802: jungfrau HW 1.0: adc output clock phase to 120 (#951) ...

* jungfrau: change adc output clock phase from 180 to 120 for v1.0 boards for reliable readout of adc #2

* formatting

2024-08-22 14:27:16 +02:00

..

include/sls

802: jungfrau HW 1.0: adc output clock phase to 120 (#951)

2024-08-22 14:27:16 +02:00

src

8.0.1.rc (#891)

2024-01-16 15:31:25 +01:00

tests

Dev/fix port size (#805)

2023-09-28 09:36:39 +02:00

CMakeLists.txt

Internal zmq using FetchContent (#780)

2023-07-17 14:20:22 +02:00