Dhanya Thattil 8a7ed30676

Dev/m3 readout speed (#985) ...

* added readoutspeed command to m3 (fullspeed - 10, half speed - 20, quarter speed - 40), removed reaodut pll, moved up system pll clock indices, leaving pll index in common altera code, default speed is half speed, allow only system_c0 to be set, the others can be obtained, same for clkphase, maxclkphaseshift, clkfreq. added to readoutspeedlist commands, updated help and updated tests

* updated readoutspeedlist command

2024-09-30 17:22:24 +02:00

..

Caller

Dev/m3 readout speed (#985)

2024-09-30 17:22:24 +02:00

CMakeLists.txt

Dev/xilinx acq (#901)

2024-02-07 13:23:08 +01:00

test-CmdParser.cpp

Dev/zmq stream all ipv6 adn remove rx_zmqip (#958)

2024-09-10 15:19:08 +02:00

test-CtbConfig.cpp

3. Dev/voltage to power (#816)

2023-10-02 11:11:28 +02:00

test-Module.cpp

tests add to namespace sls (#466)

2022-05-23 16:17:32 +02:00

test-Pattern.cpp

Pattern 6 levels (#493)

2022-07-14 12:00:07 +02:00

test-Result.cpp

formatting

2023-11-07 14:52:14 +01:00

test-SharedMemory.cpp

formatting

2023-02-14 15:08:31 +01:00

test-slsDetector.cpp

tests add to namespace sls (#466)

2022-05-23 16:17:32 +02:00