Dhanya Thattil 1d4a5d6d29
dev: jungfrau HW 1.0: adc output clock phase to 120 (#952)
* jungfrau: change adc output clock phase from 180 to 120 for v1.0 boards for reliable readout of adc #2

* versioning

* formatting
2024-08-22 15:45:41 +02:00

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C

// SPDX-License-Identifier: LGPL-3.0-or-other
// Copyright (C) 2021 Contributors to the SLS Detector Package
/** API versions */
#define RELEASE "developer"
#define APILIB "developer 0x230224"
#define APIRECEIVER "developer 0x230224"
#define APICTB "developer 0x240820"
#define APIGOTTHARD "developer 0x240820"
#define APIGOTTHARD2 "developer 0x240820"
#define APIMYTHEN3 "developer 0x240820"
#define APIMOENCH "developer 0x240820"
#define APIEIGER "developer 0x240820"
#define APIXILINXCTB "developer 0x240820"
#define APIJUNGFRAU "developer 0x240822"