detectors/slsDetectorPackage
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slsDetectorPackage/slsSupportLib
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Dhanya Thattil 1d4a5d6d29
dev: jungfrau HW 1.0: adc output clock phase to 120 (#952) 
* jungfrau: change adc output clock phase from 180 to 120 for v1.0 boards for reliable readout of adc #2

* versioning

* formatting
2024-08-22 15:45:41 +02:00
..
include/sls
dev: jungfrau HW 1.0: adc output clock phase to 120 (#952)
2024-08-22 15:45:41 +02:00
src
Xilinx ctb (#884)
2024-01-04 17:10:16 +01:00
tests
Xilinx ctb (#884)
2024-01-04 17:10:16 +01:00
CMakeLists.txt
Internal zmq using FetchContent (#780)
2023-07-17 14:20:22 +02:00