Dhanya Thattil 1d4a5d6d29

dev: jungfrau HW 1.0: adc output clock phase to 120 (#952) ...

* jungfrau: change adc output clock phase from 180 to 120 for v1.0 boards for reliable readout of adc #2

* versioning

* formatting

2024-08-22 15:45:41 +02:00

..

AD9252.h

updated all .h files with license notice and copyright notice

2021-10-14 18:10:56 +02:00

AD9257.h

dev: jungfrau HW 1.0: adc output clock phase to 120 (#952)

2024-08-22 15:45:41 +02:00

ALTERA_PLL_CYCLONE10.h

updated all .h files with license notice and copyright notice

2021-10-14 18:10:56 +02:00

ALTERA_PLL.h

Moench rw3 (#745)

2023-05-25 11:00:23 +02:00

arm64.h

Dev/xilinx acq (#901)

2024-02-07 13:23:08 +01:00

ASIC_Driver.h

updated all .h files with license notice and copyright notice

2021-10-14 18:10:56 +02:00

blackfin.h

moved verifykernelversion to common

2021-10-29 16:43:48 +02:00

clogger.h

updated all .h files with license notice and copyright notice

2021-10-14 18:10:56 +02:00

common.h

G2: reconfigure chip (#927)

2024-08-02 12:46:39 +02:00

commonServerFunctions.h

updated all .h files with license notice and copyright notice

2021-10-14 18:10:56 +02:00

communication_funcs_UDP.h

updated all .h files with license notice and copyright notice

2021-10-14 18:10:56 +02:00

communication_funcs.h

Get trimbits (#462)

2022-05-24 11:08:08 +02:00

DAC6571.h

G2: reconfigure chip (#927)

2024-08-02 12:46:39 +02:00

I2C.h

updated all .h files with license notice and copyright notice

2021-10-14 18:10:56 +02:00

INA226.h

updated all .h files with license notice and copyright notice

2021-10-14 18:10:56 +02:00

loadPattern.h

Dev/xilinx acq (#901)

2024-02-07 13:23:08 +01:00

LTC2620_Driver.h

Dev/xilinx ctb test (#942)

2024-08-20 14:33:18 +02:00

LTC2620.h

updated all .h files with license notice and copyright notice

2021-10-14 18:10:56 +02:00

MAX1932.h

updated all .h files with license notice and copyright notice

2021-10-14 18:10:56 +02:00

nios.h

moved verifykernelversion to common

2021-10-29 16:43:48 +02:00

programViaArm.h

Dev/xilinx ctb test (#942)

2024-08-20 14:33:18 +02:00

programViaBlackfin.h

Format (#506)

2022-08-05 15:39:34 +02:00

programViaNios.h

server side fixed

2021-11-08 17:24:51 +01:00

sharedMemory.h

merge from develpoer, locking complete set of start acq steps and stop steps in eiger server as it shouldnt be interrutped, moved prepare into startstatemachine (#577)

2022-11-17 14:58:53 +01:00

slsDetectorFunctionList.h

Dev/xilinx ctb test (#942)

2024-08-20 14:33:18 +02:00

slsDetectorServer_funcs.h

Dev/xilinx acq (#901)

2024-02-07 13:23:08 +01:00

UDPPacketHeaderGenerator.h

setting next frame number also for udp 1g itnerface

2022-01-28 11:44:12 +01:00