Dhanya Thattil 7d3d2a8b31 ctb and moench server: pll vco clock changed from 400 to 800,ctb server: max adc clock from 40 to 65MHz

2019-03-13 16:03:11 +01:00

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ctbDetectorServer

ctb and moench server: pll vco clock changed from 400 to 800,ctb server: max adc clock from 40 to 65MHz

2019-03-13 16:03:11 +01:00

eigerDetectorServer

updated ctb and moench, moench not tested

2019-03-05 09:38:10 +01:00

gotthardDetectorServer

client: update roi on updatedetector, (ctb, moench)moved nchans and databyte calculated to updatenumberofchannels and called for any update in roi, readoutflag or #samples changed (get should not update). ctb,moench server: roi fixed, . gotthard server: bug fix waiting to finish, ad9252 spi call fix. receiver: updated for moench and 10g

2019-03-06 17:25:18 +01:00

jungfrauDetectorServer

ctb, moench, jungfrau server: changing phase only changes one clock in one direction. ctb and moench phase shift connected to adc clk, instead of run clk

2019-03-13 08:37:45 +01:00

moenchDetectorServer

ctb and moench server: pll vco clock changed from 400 to 800,ctb server: max adc clock from 40 to 65MHz

2019-03-13 16:03:11 +01:00

slsDetectorServer

ctb moench server update: (fw update): det id changed, status reg looks at anyfifofull instead of somefifofull, datapresent looks at corresponding analog/digital fifo empty, usleep after read strobe to sync different clock

2019-03-07 17:36:35 +01:00