detectors/slsDetectorPackage
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ctb and moench server: pll vco clock changed from 400 to 800,ctb server: max adc clock from 40 to 65MHz

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This commit is contained in:
maliakal_d 2019-03-13 16:03:11 +01:00
parent 75ce111344
commit 7d3d2a8b31
2 changed files with 3 additions and 3 deletions
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4
slsDetectorServers/ctbDetectorServer/slsDetectorServer_defs.h
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@ -97,6 +97,6 @@ enum DACINDEX {D0, D1, D2, D3, D4, D5, D6, D7, D8, D9,
#define IP_PACKETSIZE (0x2032)
#define ADC_PORT_INVERT_VAL (0x453b2593)
#define MAXIMUM_ADC_CLK (40)
#define PLL_VCO_FREQ_MHZ (400)
#define MAXIMUM_ADC_CLK (65)
#define PLL_VCO_FREQ_MHZ (800)

2
slsDetectorServers/moenchDetectorServer/slsDetectorServer_defs.h
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@ -79,5 +79,5 @@ enum DACINDEX {D0, D1, D2, D3, D4, D5, D6, D7};
#define IP_PACKETSIZE (0x2032)
#define ADC_PORT_INVERT_VAL (0x453b2593) //FIXME: a default value?
#define MAXIMUM_ADC_CLK (40)
#define PLL_VCO_FREQ_MHZ (400)
#define PLL_VCO_FREQ_MHZ (800)