mirror of
https://github.com/slsdetectorgroup/slsDetectorPackage.git
synced 2025-04-23 23:10:02 +02:00
101 lines
3.9 KiB
C
101 lines
3.9 KiB
C
#pragma once
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#include "sls_detector_defs.h"
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#define REQRD_FRMWRE_VRSN 0x190000
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#define CTRL_SRVR_INIT_TIME_US (300 * 1000)
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/* Hardware Definitions */
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#define NCOUNTERS (3)
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#define MAX_COUNTER_MSK (0x7)
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#define NCHAN_1_COUNTER (128)
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#define NCHAN (128 * NCOUNTERS)
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#define NCHIP (10)
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#define NDAC (16)
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#define HV_SOFT_MAX_VOLTAGE (200)
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#define HV_HARD_MAX_VOLTAGE (530)
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#define HV_DRIVER_FILE_NAME ("/etc/devlinks/hvdac")
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#define DAC_DRIVER_FILE_NAME ("/etc/devlinks/dac")
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#define TYPE_FILE_NAME ("/etc/devlinks/type")
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#define DAC_MAX_MV (2048)
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#define TYPE_MYTHEN3_MODULE_VAL (93)
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#define TYPE_TOLERANCE (10)
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#define TYPE_NO_MODULE_STARTING_VAL (800)
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/** Default Parameters */
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#define DEFAULT_DYNAMIC_RANGE (24)
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#define DEFAULT_NUM_FRAMES (1)
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#define DEFAULT_NUM_CYCLES (1)
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#define DEFAULT_EXPTIME (100*1000*1000) //ns
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#define DEFAULT_PERIOD (2*1000*1000) //ns
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#define DEFAULT_DELAY_AFTER_TRIGGER (0)
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#define DEFAULT_HIGH_VOLTAGE (0)
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#define DEFAULT_TIMING_MODE (AUTO_TIMING)
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#define DEFAULT_READOUT_C0 (125000000) // rdo_clk, 125 MHz
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#define DEFAULT_READOUT_C1 (250000000) // rdo_x2_clk, 250 MHz
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#define DEFAULT_SYSTEM_C0 (250000000) // run_clk, 250 MHz
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#define DEFAULT_SYSTEM_C1 (125000000) // chip_clk, 125 MHz
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#define DEFAULT_SYSTEM_C2 (125000000) // sync_clk, 125 MHz
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/* Firmware Definitions */
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#define IP_HEADER_SIZE (20)
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#define FIXED_PLL_FREQUENCY (020000000) // 20MHz
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#define READOUT_PLL_VCO_FREQ_HZ (1250000000) // 1.25GHz
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#define SYSTEM_PLL_VCO_FREQ_HZ (1250000000) // 1.25GHz
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#define MAX_PATTERN_LENGTH (0x2000) // maximum number of words (64bit)
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/** Other Definitions */
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#define BIT16_MASK (0xFFFF)
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/* Enums */
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enum DACINDEX {M_CASSH, M_VTH2, M_VRFSH, M_VRFSHNPOL, M_VIPRE_OUT, M_VTH3, M_VTH1, M_VICIN, M_CAS, M_VRF, M_VPL, M_VIPRE, M_VIINSH, M_VPH, M_VTRIM, M_VDCSH};
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#define DAC_NAMES "vcassh", "vth2", "vshaper", "vshaperneg", "vipre_out", "vth3", "vth1", "vicin", "vcas", "vpreamp", "vpl", "vipre", "viinsh", "vph", "vtrim", "vdcsh"
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#define DEFAULT_DAC_VALS {1200, /* casSh */ \
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2800, /* Vth2 */ \
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1280, /* VrfSh */ \
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2800, /* VrfShNpol */ \
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1220, /* vIpreOut */ \
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2800, /* Vth3 */ \
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2800, /* Vth1 */ \
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1708, /* vIcin */ \
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1800, /* cas */ \
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1100, /* Vrf */ \
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1100, /* VPL */ \
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2624, /* vIpre */ \
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1708, /* vIinSh */ \
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1712, /* VPH */ \
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2800, /* vTrim */ \
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800 /* VdcSh */ \
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};
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enum CLKINDEX {READOUT_C0, READOUT_C1, SYSTEM_C0, SYSTEM_C1, SYSTEM_C2, NUM_CLOCKS};
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#define CLK_NAMES "READOUT_C0", "READOUT_C1", "SYSTEM_C0", "SYSTEM_C1", "SYSTEM_C2"
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enum PLLINDEX {READOUT_PLL, SYSTEM_PLL};
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/* Struct Definitions */
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typedef struct udp_header_struct {
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uint32_t udp_destmac_msb;
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uint16_t udp_srcmac_msb;
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uint16_t udp_destmac_lsb;
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uint32_t udp_srcmac_lsb;
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uint8_t ip_tos;
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uint8_t ip_ihl: 4, ip_ver: 4;
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uint16_t udp_ethertype;
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uint16_t ip_identification;
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uint16_t ip_totallength;
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uint8_t ip_protocol;
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uint8_t ip_ttl;
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uint16_t ip_fragmentoffset: 13, ip_flags: 3;
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uint16_t ip_srcip_msb;
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uint16_t ip_checksum;
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uint16_t ip_destip_msb;
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uint16_t ip_srcip_lsb;
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uint16_t udp_srcport;
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uint16_t ip_destip_lsb;
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uint16_t udp_checksum;
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uint16_t udp_destport;
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} udp_header;
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#define UDP_IP_HEADER_LENGTH_BYTES (28)
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#define PACKETS_PER_FRAME (2)
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