8cbf3c62a9
merge from developer
2020-01-22 17:30:13 +01:00
981b13494c
mythen3: virtual server, connected timing mode, row and col in header, included pattern bit and mask
2020-01-21 18:16:27 +01:00
e8bdf5a505
gotthard2: updated register map; powerchip checking detector type; internal and external period, frames, exptime; set/get delay, get actualtime, measurement, framesfromstart enabled; which detector comment updated in cmdproxy, detector and slsdetector
2020-01-16 15:33:35 +01:00
Dhanya Thattil
de53747ddd
Counters ( #71 )
...
* mythen3: adding counters mask, firmware still takes only number of counters for now
* mythen3: checking if module attached before powering on chip
* bug fix: loop inital declaration not allowed in c
* fix scope eiger test
* mythen3: renamed setCounters to setCounterMask and getCounterMask in API
* mythen3 replacing counting bits with popcount
Co-authored-by: Erik Fröjdh <erik.frojdh@gmail.com>
2020-01-14 17:40:46 +01:00
955bc74a91
mythen3: change vco freq to 1.25GHz
2019-11-21 13:38:54 +01:00
dfc886a65b
mythen3 gui
2019-11-18 17:57:19 +01:00
Marie Andrae
f53d260202
mythen3: change vph and vpl
2019-11-11 11:40:06 +01:00
2123fb47a5
mythen3: config reg enable all counters, dr
2019-11-11 10:41:42 +01:00
a92d931a8f
mythen3 frequency fixes
2019-11-07 14:35:13 +01:00
1797d39216
updated mythen3 to configure phase, freq, delay left, period left, actual time, measurement time, framesfrom start and othe register mappings
2019-11-06 18:58:22 +01:00
11ea071543
adcinvert for jungfrau, gui for jungfrau dacs
2019-10-30 12:28:51 +01:00
82570bc084
daclist and dacvalues
2019-10-30 11:09:34 +01:00
fe467cdf70
jungfrau dacs named
2019-10-29 18:11:16 +01:00
Marie Andrä
9b4fc02b0e
start/stop statemachine for my3 ( #68 )
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* start/stop statemachine for my3
* runStatus, readFrame, runBusy (use CONTROL_REG) for mythen3
* registers for Pavel
* change dac names Mythen3
2019-10-09 13:52:07 +02:00
cfd3680176
gotthard2 dacs
2019-10-08 17:10:36 +02:00
Marie Andrä
5f94b5c246
Dac ( #67 )
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* dac WIP
* dacs WIP
* DACs are working with names
* namechanges of vrfsh->vshaper, vrfshnpol->vshaperneg
* pattern for MY3, configure MAC for MY3
2019-10-07 12:13:25 +02:00
Marie Andrä
6e6fcec698
MY3.0:read and write Registers, frames, cycles, delay ( #64 )
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* MY3.0:read and write Registers, frames, cycles, delay
* write pattern seems to work
* done all corrections. added default clks: run_clk=125MHz, tick_clk=20MHz (fix), sampling_clk=80MHz (from Carlos)
* clk check for aquistition time
* clk check for aquistition time
* Update slsDetectorServer_defs.h
* Update slsDetectorFunctionList.c
2019-09-30 14:36:33 +02:00
Marie Andrä
4b987abf41
Niosmarie ( #63 )
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* HV for Mythen3 server
* HV for mythen3 server
* corrected upstreams
* missing endif
2019-09-03 09:36:02 +02:00
Marie Andrä
7a4c1161ab
add default period for mythen3 ( #56 )
2019-08-26 12:03:20 +02:00
Marie Andrä
f981825172
virtual UDP for mythen3 ( #55 )
2019-08-26 10:53:17 +02:00
4b7ab98135
initial functions for mythen3
2019-08-22 15:55:27 +02:00
72362b0334
first version of mythen3
2019-08-22 12:34:06 +02:00
