added zero trimbits to matterhorn config

slsDetectorServers/ctbDetectorServer/RegisterDefs.h

@@ -65,8 +65,8 @@
     (0x000000FF << STATUS_PT_CNTRL_STTS_OFF_OFST)
 #define STATUS_IDLE_MSK (0x677FF)
 
-/* Look at me RO register TODO */
-#define LOOK_AT_ME_REG (0x03 << MEM_MAP_SHIFT)
+/* Register containing the git hash of the FPGA firmware */
+#define FIRMWARE_GIT_HASH_REG (0x03 << MEM_MAP_SHIFT)
 
 /* System Status RO register */
 #define SYSTEM_STATUS_REG (0x04 << MEM_MAP_SHIFT)
@@ -119,7 +119,7 @@
 #define MOD_SERIAL_NUMBER_VRSN_MSK  (0x0000003F << MOD_SERIAL_NUMBER_VRSN_OFST)
 
 /* API Version RO register */
-#define API_VERSION_REG (0x0F << MEM_MAP_SHIFT)
+#define API_VERSION_REG (0x0B << MEM_MAP_SHIFT)
 
 #define API_VERSION_OFST           (0)
 #define API_VERSION_MSK            (0x00FFFFFF << API_VERSION_OFST)
@@ -128,24 +128,24 @@
 
 /* Time from Start 64 bit RO register. t = GCLK x 50 ns. Reset using
  * CONTROL_CRST. TODO */
-#define TIME_FROM_START_LSB_REG (0x10 << MEM_MAP_SHIFT)
-#define TIME_FROM_START_MSB_REG (0x11 << MEM_MAP_SHIFT)
+#define TIME_FROM_START_LSB_REG (0x97 << MEM_MAP_SHIFT)
+#define TIME_FROM_START_MSB_REG (0x98 << MEM_MAP_SHIFT)
 
 /* Delay Left 64 bit RO register. t = DLY x 50 ns. TODO */
-#define DELAY_LEFT_LSB_REG (0x12 << MEM_MAP_SHIFT)
-#define DELAY_LEFT_MSB_REG (0x13 << MEM_MAP_SHIFT)
+#define DELAY_LEFT_LSB_REG (0x8D << MEM_MAP_SHIFT)
+#define DELAY_LEFT_MSB_REG (0x8E << MEM_MAP_SHIFT)
 
 /* Triggers Left 64 bit RO register TODO */
-#define CYCLES_LEFT_LSB_REG (0x14 << MEM_MAP_SHIFT)
-#define CYCLES_LEFT_MSB_REG (0x15 << MEM_MAP_SHIFT)
+#define CYCLES_LEFT_LSB_REG (0x8F << MEM_MAP_SHIFT)
+#define CYCLES_LEFT_MSB_REG (0x90 << MEM_MAP_SHIFT)
 
 /* Frames Left 64 bit RO register TODO */
-#define FRAMES_LEFT_LSB_REG (0x16 << MEM_MAP_SHIFT)
-#define FRAMES_LEFT_MSB_REG (0x17 << MEM_MAP_SHIFT)
+#define FRAMES_LEFT_LSB_REG (0x91 << MEM_MAP_SHIFT)
+#define FRAMES_LEFT_MSB_REG (0x92 << MEM_MAP_SHIFT)
 
 /* Period Left 64 bit RO register. t = T x 50 ns. TODO */
-#define PERIOD_LEFT_LSB_REG (0x18 << MEM_MAP_SHIFT)
-#define PERIOD_LEFT_MSB_REG (0x19 << MEM_MAP_SHIFT)
+#define PERIOD_LEFT_LSB_REG (0x93 << MEM_MAP_SHIFT)
+#define PERIOD_LEFT_MSB_REG (0x94 << MEM_MAP_SHIFT)
 
 /* Exposure Time Left 64 bit RO register */
 // #define EXPTIME_LEFT_LSB_REG                (0x1A << MEM_MAP_SHIFT) // Not
@@ -160,34 +160,34 @@
 //// Not used in FW
 
 /* Data In 64 bit RO register TODO */
-#define DATA_IN_LSB_REG (0x1E << MEM_MAP_SHIFT)
-#define DATA_IN_MSB_REG (0x1F << MEM_MAP_SHIFT)
+#define DATA_IN_LSB_REG (0x10 << MEM_MAP_SHIFT)
+#define DATA_IN_MSB_REG (0x11 << MEM_MAP_SHIFT)
 
 /* Pattern Out 64 bit RO register */
-#define PATTERN_OUT_LSB_REG (0x20 << MEM_MAP_SHIFT)
-#define PATTERN_OUT_MSB_REG (0x21 << MEM_MAP_SHIFT)
+#define PATTERN_OUT_LSB_REG (0x80 << MEM_MAP_SHIFT)
+#define PATTERN_OUT_MSB_REG (0x81 << MEM_MAP_SHIFT)
 
 /* Frame number of next acquisition register (64 bit register) */
-#define NEXT_FRAME_NUMB_LOCAL_LSB_REG (0x22 << MEM_MAP_SHIFT)
-#define NEXT_FRAME_NUMB_LOCAL_MSB_REG (0x23 << MEM_MAP_SHIFT)
+#define NEXT_FRAME_NUMB_LOCAL_LSB_REG (0x12 << MEM_MAP_SHIFT)
+#define NEXT_FRAME_NUMB_LOCAL_MSB_REG (0x13 << MEM_MAP_SHIFT)
 
 /* Frames From Start PG 64 bit RO register. Reset using CONTROL_CRST. TODO */
-#define FRAMES_FROM_START_PG_LSB_REG (0x24 << MEM_MAP_SHIFT)
-#define FRAMES_FROM_START_PG_MSB_REG (0x25 << MEM_MAP_SHIFT)
+#define FRAMES_FROM_START_PG_LSB_REG (0x99 << MEM_MAP_SHIFT)
+#define FRAMES_FROM_START_PG_MSB_REG (0x9A << MEM_MAP_SHIFT)
 
 /* Start Frame Time (Measurement Time) 64 bit register (timestamp at a frame
  * start until reset) TODO */
-#define START_FRAME_TIME_LSB_REG (0x26 << MEM_MAP_SHIFT)
-#define START_FRAME_TIME_MSB_REG (0x27 << MEM_MAP_SHIFT)
+#define START_FRAME_TIME_LSB_REG (0x9B << MEM_MAP_SHIFT)
+#define START_FRAME_TIME_MSB_REG (0x9C << MEM_MAP_SHIFT)
 
 /* Power Status RO register */
-#define POWER_STATUS_REG (0x29 << MEM_MAP_SHIFT)
+#define POWER_STATUS_REG (0x18 << MEM_MAP_SHIFT)
 
 #define POWER_STATUS_ALRT_OFST (27)
 #define POWER_STATUS_ALRT_MSK  (0x0000001F << POWER_STATUS_ALRT_OFST)
 
 /* FIFO Transceiver In Status RO register */
-#define FIFO_TIN_STATUS_REG                 (0x30 << MEM_MAP_SHIFT)
+#define FIFO_TIN_STATUS_REG                 (0x1A << MEM_MAP_SHIFT)
 #define FIFO_TIN_STATUS_FIFO_EMPTY_1_OFST   (4)
 #define FIFO_TIN_STATUS_FIFO_EMPTY_1_MSK    (0x00000001 << FIFO_TIN_STATUS_FIFO_EMPTY_1_OFST)
 #define FIFO_TIN_STATUS_FIFO_EMPTY_2_OFST   (5)
@@ -198,23 +198,54 @@
 #define FIFO_TIN_STATUS_FIFO_EMPTY_4_MSK    (0x00000001 << FIFO_TIN_STATUS_FIFO_EMPTY_4_OFST)
 #define FIFO_TIN_STATUS_FIFO_EMPTY_ALL_MSK  (0x0000000F << FIFO_TIN_STATUS_FIFO_EMPTY_1_OFST)
 
+/* FIFO Transceiver Fill level RO register */
+#define FIFO_TIN_FILL_REG                   (0x25 << MEM_MAP_SHIFT)
+#define FIFO_TIN_FILL_FIFO_1_OFST           (0)
+#define FIFO_TIN_FILL_FIFO_1_MSK            (0x00003FFF << FIFO_TIN_FILL_FIFO__1_OFST)
+#define FIFO_TIN_FILL_FIFO_2_OFST           (16)
+#define FIFO_TIN_FILL_FIFO_2_MSK            (0x00003FFF << FIFO_TIN_FILL_FIFO__2_OFST)
+
+/* FIFO ADC Fill level RO register */
+#define FIFO_ADC_FILL_REG                   (0x26 << MEM_MAP_SHIFT)
+#define FIFO_ADC_FILL_FIFO_OFST             (0)
+#define FIFO_ADC_FILL_FIFO_MSK              (0x00003FFF << FIFO_ADC_FILL_FIFO_OFST)
+
+/* Enable continuos readout register */
+#define CONTINUOUS_RO_ENABLE_REG            (0x27 << MEM_MAP_SHIFT)
+#define CONTINUOUS_RO_ADC_ENABLE_OFST       (0)
+#define CONTINUOUS_RO_TIN_ENABLE_OFST       (1)
+#define CONTINUOUS_RO_DBIT_ENABLE_OFST      (2)
+#define CONTINUOUS_RO_ADC_ENABLE_MSK        (0x00000001 << CONTINUOUS_RO_ADC_ENABLE_OFST)
+#define CONTINUOUS_RO_TIN_ENABLE_MSK        (0x00000001 << CONTINUOUS_RO_TIN_ENABLE_OFST)
+#define CONTINUOUS_RO_DBIT_ENABLE_MSK       (0x00000001 << CONTINUOUS_RO_DBIT_ENABLE_OFST)
+#define DBIT_INJECT_COUNTER_ENA_OFST        (3) // continuously injects fake-data into the dbit fifo when enabled. 
+#define DBIT_INJECT_COUNTER_ENA_MSK         (0x00000001 << DBIT_INJECT_COUNTER_ENA_OFST)
+#define DBIT_INJECT_COUNTER_CLKDIV_OFST     (8) // Additional clock divider for fake-data injection
+#define DBIT_INJECT_COUNTER_CLKDIV_MSK      (0x000000FF << DBIT_INJECT_COUNTER_CLKDIV_OFST)
+
+/* 64-bit FPGA chip ID. Unique for every device. read-only */
+#define FPGA_chipID_0_REG                       (0x28 << MEM_MAP_SHIFT)
+#define FPGA_chipID_1_REG                       (0x29 << MEM_MAP_SHIFT)
+
 /* FIFO Transceiver In 64 bit RO register */
-#define FIFO_TIN_LSB_REG (0x31 << MEM_MAP_SHIFT)
-#define FIFO_TIN_MSB_REG (0x32 << MEM_MAP_SHIFT)
+#define FIFO_TIN_LSB_REG (0x1B << MEM_MAP_SHIFT)
+#define FIFO_TIN_MSB_REG (0x1C << MEM_MAP_SHIFT)
 
 /* FIFO Digital In Status RO register */
-#define FIFO_DIN_STATUS_REG             (0x3B << MEM_MAP_SHIFT)
+#define FIFO_DIN_STATUS_REG             (0x1D << MEM_MAP_SHIFT)
+#define FIFO_DIN_STATUS_FIFO_FILL_OFST  (0)
+#define FIFO_DIN_STATUS_FIFO_FILL_MSK   (0x00003FFF)
 #define FIFO_DIN_STATUS_FIFO_FULL_OFST  (30)
 #define FIFO_DIN_STATUS_FIFO_FULL_MSK   (0x00000001 << FIFO_DIN_STATUS_FIFO_FULL_OFST)
 #define FIFO_DIN_STATUS_FIFO_EMPTY_OFST (31)
 #define FIFO_DIN_STATUS_FIFO_EMPTY_MSK  (0x00000001 << FIFO_DIN_STATUS_FIFO_EMPTY_OFST)
 
 /* FIFO Digital In 64 bit RO register */
-#define FIFO_DIN_LSB_REG (0x3C << MEM_MAP_SHIFT)
-#define FIFO_DIN_MSB_REG (0x3D << MEM_MAP_SHIFT)
+#define FIFO_DIN_LSB_REG (0x1E << MEM_MAP_SHIFT)
+#define FIFO_DIN_MSB_REG (0x1F << MEM_MAP_SHIFT)
 
 /* SPI (Serial Peripheral Interface) DAC, HV RW register */
-#define SPI_REG (0x40 << MEM_MAP_SHIFT)
+#define SPI_REG (0x20 << MEM_MAP_SHIFT)
 
 #define SPI_DAC_SRL_DGTL_OTPT_OFST (0)
 #define SPI_DAC_SRL_DGTL_OTPT_MSK  (0x00000001 << SPI_DAC_SRL_DGTL_OTPT_OFST)
@@ -230,7 +261,7 @@
 #define SPI_HV_SRL_CS_OTPT_MSK     (0x00000001 << SPI_HV_SRL_CS_OTPT_OFST)
 
 /* ADC SPI (Serial Peripheral Interface) RW register */
-#define ADC_SPI_REG (0x41 << MEM_MAP_SHIFT)
+#define ADC_SPI_REG (0x21 << MEM_MAP_SHIFT)
 
 #define ADC_SPI_SRL_CLK_OTPT_OFST (0)
 #define ADC_SPI_SRL_CLK_OTPT_MSK  (0x00000001 << ADC_SPI_SRL_CLK_OTPT_OFST)
@@ -240,7 +271,7 @@
 #define ADC_SPI_SRL_CS_OTPT_MSK   (0x0000000F << ADC_SPI_SRL_CS_OTPT_OFST)
 
 /* ADC Offset RW register */
-#define ADC_OFFSET_REG (0x42 << MEM_MAP_SHIFT)
+#define ADC_OFFSET_REG (0x22 << MEM_MAP_SHIFT)
 
 #define ADC_OFFSET_ADC_PPLN_OFST (0)
 #define ADC_OFFSET_ADC_PPLN_MSK  (0x000000FF << ADC_OFFSET_ADC_PPLN_OFST)
@@ -248,7 +279,7 @@
 #define ADC_OFFSET_DBT_PPLN_MSK  (0x000000FF << ADC_OFFSET_DBT_PPLN_OFST)
 
 /* ADC Port Invert RW register */
-#define ADC_PORT_INVERT_REG (0x43 << MEM_MAP_SHIFT)
+#define ADC_PORT_INVERT_REG (0x23 << MEM_MAP_SHIFT)
 
 #define ADC_PORT_INVERT_0_INPT_OFST (0)
 #define ADC_PORT_INVERT_0_INPT_MSK  (0x000000FF << ADC_PORT_INVERT_0_INPT_OFST)
@@ -260,7 +291,7 @@
 #define ADC_PORT_INVERT_3_INPT_MSK  (0x000000FF << ADC_PORT_INVERT_3_INPT_OFST)
 
 /* Dummy RW register */
-#define DUMMY_REG (0x44 << MEM_MAP_SHIFT)
+#define DUMMY_REG (0x24 << MEM_MAP_SHIFT)
 
 #define DUMMY_FIFO_CHNNL_SLCT_OFST          (0)
 #define DUMMY_FIFO_CHNNL_SLCT_MSK           (0x0000003F << DUMMY_FIFO_CHNNL_SLCT_OFST)
@@ -273,46 +304,8 @@
 #define DUMMY_TRNSCVR_FIFO_RD_STRBE_OFST    (14)
 #define DUMMY_TRNSCVR_FIFO_RD_STRBE_MSK     (0x00000001 << DUMMY_TRNSCVR_FIFO_RD_STRBE_OFST)
 
-/* Receiver IP Address RW register */
-#define RX_IP_REG (0x45 << MEM_MAP_SHIFT)
-
-/* UDP Port RW register */
-#define UDP_PORT_REG (0x46 << MEM_MAP_SHIFT)
-
-#define UDP_PORT_RX_OFST (0)
-#define UDP_PORT_RX_MSK  (0x0000FFFF << UDP_PORT_RX_OFST)
-#define UDP_PORT_TX_OFST (16)
-#define UDP_PORT_TX_MSK  (0x0000FFFF << UDP_PORT_TX_OFST)
-
-/* Receiver Mac Address 64 bit RW register */
-#define RX_MAC_LSB_REG (0x47 << MEM_MAP_SHIFT)
-#define RX_MAC_MSB_REG (0x48 << MEM_MAP_SHIFT)
-
-#define RX_MAC_LSB_OFST (0)
-#define RX_MAC_LSB_MSK  (0xFFFFFFFF << RX_MAC_LSB_OFST)
-#define RX_MAC_MSB_OFST (0)
-#define RX_MAC_MSB_MSK  (0x0000FFFF << RX_MAC_MSB_OFST)
-
-/* Detector/ Transmitter Mac Address 64 bit RW register */
-#define TX_MAC_LSB_REG (0x49 << MEM_MAP_SHIFT)
-#define TX_MAC_MSB_REG (0x4A << MEM_MAP_SHIFT)
-
-#define TX_MAC_LSB_OFST (0)
-#define TX_MAC_LSB_MSK  (0xFFFFFFFF << TX_MAC_LSB_OFST)
-#define TX_MAC_MSB_OFST (0)
-#define TX_MAC_MSB_MSK  (0x0000FFFF << TX_MAC_MSB_OFST)
-
-/* Detector/ Transmitter IP Address RW register */
-#define TX_IP_REG (0x4B << MEM_MAP_SHIFT)
-
-/* Detector/ Transmitter IP Checksum RW register */
-#define TX_IP_CHECKSUM_REG (0x4C << MEM_MAP_SHIFT)
-
-#define TX_IP_CHECKSUM_OFST (0)
-#define TX_IP_CHECKSUM_MSK  (0x0000FFFF << TX_IP_CHECKSUM_OFST)
-
 /* Configuration RW register */
-#define CONFIG_REG (0x4D << MEM_MAP_SHIFT)
+#define CONFIG_REG (0x2D << MEM_MAP_SHIFT)
 
 #define CONFIG_LED_DSBL_OFST           (0)
 #define CONFIG_LED_DSBL_MSK            (0x00000001 << CONFIG_LED_DSBL_OFST)
@@ -327,7 +320,7 @@
 #define CONFIG_GB10_SND_UDP_MSK  (0x00000001 << CONFIG_GB10_SND_UDP_OFST)
 
 /* External Signal RW register */
-#define EXT_SIGNAL_REG (0x4E << MEM_MAP_SHIFT)
+#define EXT_SIGNAL_REG (0x2E << MEM_MAP_SHIFT)
 
 #define EXT_SIGNAL_OFST      (0)
 #define EXT_SIGNAL_MSK       (0x00000001 << EXT_SIGNAL_OFST)
@@ -335,7 +328,7 @@
 #define EXT_SIGNAL_TRGGR_VAL ((0x1 << EXT_SIGNAL_OFST) & EXT_SIGNAL_MSK)
 
 /* Control RW register */
-#define CONTROL_REG (0x4F << MEM_MAP_SHIFT)
+#define CONTROL_REG (0x2F << MEM_MAP_SHIFT)
 
 #define CONTROL_STRT_ACQSTN_OFST (0)
 #define CONTROL_STRT_ACQSTN_MSK  (0x00000001 << CONTROL_STRT_ACQSTN_OFST)
@@ -375,10 +368,10 @@
 #define CONTROL_CLR_ACQSTN_FIFO_MSK  (0x00000001 << CONTROL_CLR_ACQSTN_FIFO_OFST)
 
 /* Reconfiguratble PLL Paramater RW register */
-#define PLL_PARAM_REG (0x50 << MEM_MAP_SHIFT)
+#define PLL_PARAM_REG (0x30 << MEM_MAP_SHIFT)
 
 /* Reconfiguratble PLL Control RW regiser */
-#define PLL_CNTRL_REG (0x51 << MEM_MAP_SHIFT)
+#define PLL_CNTRL_REG (0x31 << MEM_MAP_SHIFT)
 
 #define PLL_CNTRL_RCNFG_PRMTR_RST_OFST (0)
 #define PLL_CNTRL_RCNFG_PRMTR_RST_MSK                                          \
@@ -391,7 +384,7 @@
 #define PLL_CNTRL_ADDR_MSK      (0x0000003F << PLL_CNTRL_ADDR_OFST)
 
 /* Pattern Control RW register */
-#define PATTERN_CNTRL_REG (0x52 << MEM_MAP_SHIFT)
+#define PATTERN_CNTRL_REG (0x88 << MEM_MAP_SHIFT)
 
 #define PATTERN_CNTRL_WR_OFST   (0)
 #define PATTERN_CNTRL_WR_MSK    (0x00000001 << PATTERN_CNTRL_WR_OFST)
@@ -401,7 +394,7 @@
 #define PATTERN_CNTRL_ADDR_MSK  (0x00001FFF << PATTERN_CNTRL_ADDR_OFST)
 
 /* Pattern Limit RW regiser */
-#define PATTERN_LIMIT_REG (0x53 << MEM_MAP_SHIFT)
+#define PATTERN_LIMIT_REG (0x89 << MEM_MAP_SHIFT)
 
 #define PATTERN_LIMIT_STRT_OFST (0)
 #define PATTERN_LIMIT_STRT_MSK  (0x00001FFF << PATTERN_LIMIT_STRT_OFST)
@@ -409,7 +402,7 @@
 #define PATTERN_LIMIT_STP_MSK   (0x00001FFF << PATTERN_LIMIT_STP_OFST)
 
 /* Pattern Loop 0 Address RW regiser */
-#define PATTERN_LOOP_0_ADDR_REG (0x54 << MEM_MAP_SHIFT)
+#define PATTERN_LOOP_0_ADDR_REG (0xA0 << MEM_MAP_SHIFT)
 
 #define PATTERN_LOOP_0_ADDR_STRT_OFST (0)
 #define PATTERN_LOOP_0_ADDR_STRT_MSK                                           \
@@ -418,10 +411,10 @@
 #define PATTERN_LOOP_0_ADDR_STP_MSK  (0x00001FFF << PATTERN_LOOP_0_ADDR_STP_OFST)
 
 /* Pattern Loop 0 Iteration RW regiser */
-#define PATTERN_LOOP_0_ITERATION_REG (0x55 << MEM_MAP_SHIFT)
+#define PATTERN_LOOP_0_ITERATION_REG (0xA1 << MEM_MAP_SHIFT)
 
 /* Pattern Loop 1 Address RW regiser */
-#define PATTERN_LOOP_1_ADDR_REG (0x56 << MEM_MAP_SHIFT)
+#define PATTERN_LOOP_1_ADDR_REG (0xA5 << MEM_MAP_SHIFT)
 
 #define PATTERN_LOOP_1_ADDR_STRT_OFST (0)
 #define PATTERN_LOOP_1_ADDR_STRT_MSK                                           \
@@ -430,10 +423,10 @@
 #define PATTERN_LOOP_1_ADDR_STP_MSK  (0x00001FFF << PATTERN_LOOP_1_ADDR_STP_OFST)
 
 /* Pattern Loop 1 Iteration RW regiser */
-#define PATTERN_LOOP_1_ITERATION_REG (0x57 << MEM_MAP_SHIFT)
+#define PATTERN_LOOP_1_ITERATION_REG (0xA6 << MEM_MAP_SHIFT)
 
 /* Pattern Loop 2 Address RW regiser */
-#define PATTERN_LOOP_2_ADDR_REG (0x58 << MEM_MAP_SHIFT)
+#define PATTERN_LOOP_2_ADDR_REG (0xAA << MEM_MAP_SHIFT)
 
 #define PATTERN_LOOP_2_ADDR_STRT_OFST (0)
 #define PATTERN_LOOP_2_ADDR_STRT_MSK                                           \
@@ -442,29 +435,29 @@
 #define PATTERN_LOOP_2_ADDR_STP_MSK  (0x00001FFF << PATTERN_LOOP_2_ADDR_STP_OFST)
 
 /* Pattern Loop 2 Iteration RW regiser */
-#define PATTERN_LOOP_2_ITERATION_REG (0x59 << MEM_MAP_SHIFT)
+#define PATTERN_LOOP_2_ITERATION_REG (0xAB << MEM_MAP_SHIFT)
 
 /* Pattern Wait 0 RW regiser */
-#define PATTERN_WAIT_0_ADDR_REG (0x5A << MEM_MAP_SHIFT)
+#define PATTERN_WAIT_0_ADDR_REG (0xA2 << MEM_MAP_SHIFT)
 
 #define PATTERN_WAIT_0_ADDR_OFST (0)
 #define PATTERN_WAIT_0_ADDR_MSK  (0x00001FFF << PATTERN_WAIT_0_ADDR_OFST)
 // FIXME: is mask 3FF
 
 /* Pattern Wait 1 RW regiser */
-#define PATTERN_WAIT_1_ADDR_REG (0x5B << MEM_MAP_SHIFT)
+#define PATTERN_WAIT_1_ADDR_REG (0xA7 << MEM_MAP_SHIFT)
 
 #define PATTERN_WAIT_1_ADDR_OFST (0)
 #define PATTERN_WAIT_1_ADDR_MSK  (0x00001FFF << PATTERN_WAIT_1_ADDR_OFST)
 
 /* Pattern Wait 2 RW regiser */
-#define PATTERN_WAIT_2_ADDR_REG (0x5C << MEM_MAP_SHIFT)
+#define PATTERN_WAIT_2_ADDR_REG (0xAC << MEM_MAP_SHIFT)
 
 #define PATTERN_WAIT_2_ADDR_OFST (0)
 #define PATTERN_WAIT_2_ADDR_MSK  (0x00001FFF << PATTERN_WAIT_2_ADDR_OFST)
 
 /* Samples RW register */
-#define SAMPLES_REG (0x5D << MEM_MAP_SHIFT)
+#define SAMPLES_REG (0x32 << MEM_MAP_SHIFT)
 
 #define SAMPLES_DIGITAL_OFST (0)
 #define SAMPLES_DIGITAL_MSK  (0x0000FFFF << SAMPLES_DIGITAL_OFST)
@@ -472,7 +465,7 @@
 #define SAMPLES_ANALOG_MSK   (0x0000FFFF << SAMPLES_ANALOG_OFST)
 
 /** Power RW register */
-#define POWER_REG (0x5E << MEM_MAP_SHIFT)
+#define POWER_REG (0x33 << MEM_MAP_SHIFT)
 
 #define POWER_ENBL_VLTG_RGLTR_OFST  (16)
 #define POWER_ENBL_VLTG_RGLTR_MSK   (0x0000001F << POWER_ENBL_VLTG_RGLTR_OFST)
@@ -480,25 +473,25 @@
 #define POWER_HV_INTERNAL_SLCT_MSK  (0x00000001 << POWER_HV_INTERNAL_SLCT_OFST)
 
 /* Number of samples from transceiver RW register */
-#define SAMPLES_TRANSCEIVER_REG  (0x5F << MEM_MAP_SHIFT)
+#define SAMPLES_TRANSCEIVER_REG  (0x34 << MEM_MAP_SHIFT)
 #define SAMPLES_TRANSCEIVER_OFST (0)
 #define SAMPLES_TRANSCEIVER_MSK  (0x0000FFFF << SAMPLES_TRANSCEIVER_OFST)
 
 /* Delay 64 bit RW register. t = DLY x 50 ns. */
-#define DELAY_LSB_REG (0x60 << MEM_MAP_SHIFT)
-#define DELAY_MSB_REG (0x61 << MEM_MAP_SHIFT)
+#define DELAY_LSB_REG (0x8D << MEM_MAP_SHIFT)
+#define DELAY_MSB_REG (0x8E << MEM_MAP_SHIFT)
 
 /* Triggers 64 bit RW register */
-#define CYCLES_LSB_REG (0x62 << MEM_MAP_SHIFT)
-#define CYCLES_MSB_REG (0x63 << MEM_MAP_SHIFT)
+#define CYCLES_LSB_REG (0x8F << MEM_MAP_SHIFT)
+#define CYCLES_MSB_REG (0x90 << MEM_MAP_SHIFT)
 
 /* Frames 64 bit RW register */
-#define FRAMES_LSB_REG (0x64 << MEM_MAP_SHIFT)
-#define FRAMES_MSB_REG (0x65 << MEM_MAP_SHIFT)
+#define FRAMES_LSB_REG (0x91 << MEM_MAP_SHIFT)
+#define FRAMES_MSB_REG (0x92 << MEM_MAP_SHIFT)
 
 /* Period 64 bit RW register */
-#define PERIOD_LSB_REG (0x66 << MEM_MAP_SHIFT)
-#define PERIOD_MSB_REG (0x67 << MEM_MAP_SHIFT)
+#define PERIOD_LSB_REG (0x93 << MEM_MAP_SHIFT)
+#define PERIOD_MSB_REG (0x94 << MEM_MAP_SHIFT)
 
 /* Period 64 bit RW register */
 // #define EXPTIME_LSB_REG    			    (0x68 << MEM_MAP_SHIFT) //
@@ -513,33 +506,27 @@
 
 /* Pattern IO Control 64 bit RW regiser
  * Each bit configured as output(1)/ input(0) */
-#define PATTERN_IO_CNTRL_LSB_REG (0x6C << MEM_MAP_SHIFT)
-#define PATTERN_IO_CNTRL_MSB_REG (0x6D << MEM_MAP_SHIFT)
-
-/* Pattern IO Clock Control 64 bit RW regiser
- * When bit n enabled (1), clocked output for DIO[n] (T run clock)
- * When bit n disabled (0), Dio[n] driven by its pattern output */
-#define PATTERN_IO_CLK_CNTRL_LSB_REG (0x6E << MEM_MAP_SHIFT)
-#define PATTERN_IO_CLK_CNTRL_MSB_REG (0x6F << MEM_MAP_SHIFT)
+#define PATTERN_IO_CNTRL_LSB_REG (0x8A << MEM_MAP_SHIFT)
+#define PATTERN_IO_CNTRL_MSB_REG (0x8B << MEM_MAP_SHIFT)
 
 /* Pattern In 64 bit RW register */
-#define PATTERN_IN_LSB_REG (0x70 << MEM_MAP_SHIFT)
-#define PATTERN_IN_MSB_REG (0x71 << MEM_MAP_SHIFT)
+#define PATTERN_IN_LSB_REG (0x82 << MEM_MAP_SHIFT)
+#define PATTERN_IN_MSB_REG (0x83 << MEM_MAP_SHIFT)
 
 /* Pattern Wait Timer 0 64 bit RW register. t = PWT1 x T run clock */
-#define PATTERN_WAIT_TIMER_0_LSB_REG (0x72 << MEM_MAP_SHIFT)
-#define PATTERN_WAIT_TIMER_0_MSB_REG (0x73 << MEM_MAP_SHIFT)
+#define PATTERN_WAIT_TIMER_0_LSB_REG (0xA3 << MEM_MAP_SHIFT)
+#define PATTERN_WAIT_TIMER_0_MSB_REG (0xA4 << MEM_MAP_SHIFT)
 
 /* Pattern Wait Timer 1 64 bit RW register. t = PWT2 x T run clock */
-#define PATTERN_WAIT_TIMER_1_LSB_REG (0x74 << MEM_MAP_SHIFT)
-#define PATTERN_WAIT_TIMER_1_MSB_REG (0x75 << MEM_MAP_SHIFT)
+#define PATTERN_WAIT_TIMER_1_LSB_REG (0xA8 << MEM_MAP_SHIFT)
+#define PATTERN_WAIT_TIMER_1_MSB_REG (0xA9 << MEM_MAP_SHIFT)
 
 /* Pattern Wait Timer 2 64 bit RW register. t = PWT3 x T run clock */
-#define PATTERN_WAIT_TIMER_2_LSB_REG (0x76 << MEM_MAP_SHIFT)
-#define PATTERN_WAIT_TIMER_2_MSB_REG (0x77 << MEM_MAP_SHIFT)
+#define PATTERN_WAIT_TIMER_2_LSB_REG (0xAD << MEM_MAP_SHIFT)
+#define PATTERN_WAIT_TIMER_2_MSB_REG (0xAE << MEM_MAP_SHIFT)
 
 /* Readout enable RW register */
-#define READOUT_10G_ENABLE_REG (0x79 << MEM_MAP_SHIFT)
+#define READOUT_10G_ENABLE_REG (0x3C << MEM_MAP_SHIFT)
 
 #define READOUT_10G_ENABLE_ANLG_OFST    (0)
 #define READOUT_10G_ENABLE_ANLG_MSK     (0x000000FF << READOUT_10G_ENABLE_ANLG_OFST)
@@ -550,7 +537,7 @@
     (0x0000000F << READOUT_10G_ENABLE_TRNSCVR_OFST)
 
 /* Digital Bit External Trigger RW register */
-#define DBIT_EXT_TRG_REG (0x7B << MEM_MAP_SHIFT)
+#define DBIT_EXT_TRG_REG (0x3E << MEM_MAP_SHIFT)
 
 #define DBIT_EXT_TRG_SRC_OFST      (0)
 #define DBIT_EXT_TRG_SRC_MSK       (0x0000003F << DBIT_EXT_TRG_SRC_OFST)
@@ -558,7 +545,7 @@
 #define DBIT_EXT_TRG_OPRTN_MD_MSK  (0x00000001 << DBIT_EXT_TRG_OPRTN_MD_OFST)
 
 /* Pin Delay 0 RW register */
-#define OUTPUT_DELAY_0_REG              (0x7C << MEM_MAP_SHIFT)
+#define OUTPUT_DELAY_0_REG              (0x3F << MEM_MAP_SHIFT)
 #define OUTPUT_DELAY_0_OTPT_STTNG_STEPS (25)
 #define OUTPUT_DELAY_0_OTPT_STTNG_OFST                                         \
     (0) // t = OTPT_STTNG * 25 ps, max for Cyclone V = 775 ps
@@ -574,18 +561,18 @@
 
 /* Pin Delay 1 RW register
  * Each bit configured as enable for dynamic output delay configuration */
-#define PIN_DELAY_1_REG (0x7D << MEM_MAP_SHIFT)
+#define PIN_DELAY_1_REG (0x40 << MEM_MAP_SHIFT)
 
 /** Pattern Mask 64 bit RW regiser */
-#define PATTERN_MASK_LSB_REG (0x80 << MEM_MAP_SHIFT)
-#define PATTERN_MASK_MSB_REG (0x81 << MEM_MAP_SHIFT)
+#define PATTERN_MASK_LSB_REG (0x84 << MEM_MAP_SHIFT)
+#define PATTERN_MASK_MSB_REG (0x85 << MEM_MAP_SHIFT)
 
 /** Pattern Set 64 bit RW regiser */
-#define PATTERN_SET_LSB_REG (0x82 << MEM_MAP_SHIFT)
-#define PATTERN_SET_MSB_REG (0x83 << MEM_MAP_SHIFT)
+#define PATTERN_SET_LSB_REG (0x86 << MEM_MAP_SHIFT)
+#define PATTERN_SET_MSB_REG (0x87 << MEM_MAP_SHIFT)
 
 /* Pattern Loop 3 Address RW regiser */
-#define PATTERN_LOOP_3_ADDR_REG (0x84 << MEM_MAP_SHIFT)
+#define PATTERN_LOOP_3_ADDR_REG (0xAF << MEM_MAP_SHIFT)
 
 #define PATTERN_LOOP_3_ADDR_STRT_OFST (0)
 #define PATTERN_LOOP_3_ADDR_STRT_MSK                                           \
@@ -594,10 +581,10 @@
 #define PATTERN_LOOP_3_ADDR_STP_MSK  (0x00001FFF << PATTERN_LOOP_3_ADDR_STP_OFST)
 
 /* Pattern Loop 3 Iteration RW regiser */
-#define PATTERN_LOOP_3_ITERATION_REG (0x85 << MEM_MAP_SHIFT)
+#define PATTERN_LOOP_3_ITERATION_REG (0xB0 << MEM_MAP_SHIFT)
 
 /* Pattern Loop 4 Address RW regiser */
-#define PATTERN_LOOP_4_ADDR_REG (0x86 << MEM_MAP_SHIFT)
+#define PATTERN_LOOP_4_ADDR_REG (0xB4 << MEM_MAP_SHIFT)
 
 #define PATTERN_LOOP_4_ADDR_STRT_OFST (0)
 #define PATTERN_LOOP_4_ADDR_STRT_MSK                                           \
@@ -606,10 +593,10 @@
 #define PATTERN_LOOP_4_ADDR_STP_MSK  (0x00001FFF << PATTERN_LOOP_4_ADDR_STP_OFST)
 
 /* Pattern Loop 4 Iteration RW regiser */
-#define PATTERN_LOOP_4_ITERATION_REG (0x87 << MEM_MAP_SHIFT)
+#define PATTERN_LOOP_4_ITERATION_REG (0xB5 << MEM_MAP_SHIFT)
 
 /* Pattern Loop 5 Address RW regiser */
-#define PATTERN_LOOP_5_ADDR_REG (0x88 << MEM_MAP_SHIFT)
+#define PATTERN_LOOP_5_ADDR_REG (0xB9 << MEM_MAP_SHIFT)
 
 #define PATTERN_LOOP_5_ADDR_STRT_OFST (0)
 #define PATTERN_LOOP_5_ADDR_STRT_MSK                                           \
@@ -618,43 +605,43 @@
 #define PATTERN_LOOP_5_ADDR_STP_MSK  (0x00001FFF << PATTERN_LOOP_5_ADDR_STP_OFST)
 
 /* Pattern Loop 5 Iteration RW regiser */
-#define PATTERN_LOOP_5_ITERATION_REG (0x89 << MEM_MAP_SHIFT)
+#define PATTERN_LOOP_5_ITERATION_REG (0xBA << MEM_MAP_SHIFT)
 
 /* Pattern Wait 3 RW regiser */
-#define PATTERN_WAIT_3_ADDR_REG (0x8A << MEM_MAP_SHIFT)
+#define PATTERN_WAIT_3_ADDR_REG (0xB1 << MEM_MAP_SHIFT)
 
 #define PATTERN_WAIT_3_ADDR_OFST (0)
 #define PATTERN_WAIT_3_ADDR_MSK  (0x00001FFF << PATTERN_WAIT_3_ADDR_OFST)
 
 /* Pattern Wait 4 RW regiser */
-#define PATTERN_WAIT_4_ADDR_REG (0x8B << MEM_MAP_SHIFT)
+#define PATTERN_WAIT_4_ADDR_REG (0xB6 << MEM_MAP_SHIFT)
 
 #define PATTERN_WAIT_4_ADDR_OFST (0)
 #define PATTERN_WAIT_4_ADDR_MSK  (0x00001FFF << PATTERN_WAIT_4_ADDR_OFST)
 
 /* Pattern Wait 5 RW regiser */
-#define PATTERN_WAIT_5_ADDR_REG (0x8C << MEM_MAP_SHIFT)
+#define PATTERN_WAIT_5_ADDR_REG (0xBB << MEM_MAP_SHIFT)
 
 #define PATTERN_WAIT_5_ADDR_OFST (0)
 #define PATTERN_WAIT_5_ADDR_MSK  (0x00001FFF << PATTERN_WAIT_5_ADDR_OFST)
 
 /* Pattern Wait Timer 3 64 bit RW register. t = PWT1 x T run clock */
-#define PATTERN_WAIT_TIMER_3_LSB_REG (0x8D << MEM_MAP_SHIFT)
-#define PATTERN_WAIT_TIMER_3_MSB_REG (0x8E << MEM_MAP_SHIFT)
+#define PATTERN_WAIT_TIMER_3_LSB_REG (0xB2 << MEM_MAP_SHIFT)
+#define PATTERN_WAIT_TIMER_3_MSB_REG (0xB3 << MEM_MAP_SHIFT)
 
 /* Pattern Wait Timer 4 64 bit RW register. t = PWT1 x T run clock */
-#define PATTERN_WAIT_TIMER_4_LSB_REG (0x8F << MEM_MAP_SHIFT)
-#define PATTERN_WAIT_TIMER_4_MSB_REG (0x90 << MEM_MAP_SHIFT)
+#define PATTERN_WAIT_TIMER_4_LSB_REG (0xB7 << MEM_MAP_SHIFT)
+#define PATTERN_WAIT_TIMER_4_MSB_REG (0xB8 << MEM_MAP_SHIFT)
 
 /* Pattern Wait Timer 5 64 bit RW register. t = PWT1 x T run clock */
-#define PATTERN_WAIT_TIMER_5_LSB_REG (0x91 << MEM_MAP_SHIFT)
-#define PATTERN_WAIT_TIMER_5_MSB_REG (0x92 << MEM_MAP_SHIFT)
+#define PATTERN_WAIT_TIMER_5_LSB_REG (0xBC << MEM_MAP_SHIFT)
+#define PATTERN_WAIT_TIMER_5_MSB_REG (0xBD << MEM_MAP_SHIFT)
 
 /* Slow ADC SPI Value RO register */
-#define ADC_SLOW_DATA_REG (0x93 << MEM_MAP_SHIFT)
+#define ADC_SLOW_DATA_REG (0x41 << MEM_MAP_SHIFT)
 
 /* Slow ADC SPI Value Config register */
-#define ADC_SLOW_CFG_REG (0x94 << MEM_MAP_SHIFT)
+#define ADC_SLOW_CFG_REG (0x42 << MEM_MAP_SHIFT)
 /** Read back CFG Register */
 #define ADC_SLOW_CFG_RB_OFST (2)
 #define ADC_SLOW_CFG_RB_MSK  (0x00000001 << ADC_SLOW_CFG_RB_OFST)
@@ -733,7 +720,7 @@
     ((0x1 << ADC_SLOW_CFG_CFG_OFST) & ADC_SLOW_CFG_CFG_MSK)
 
 /* Slow ADC SPI Value Control register */
-#define ADC_SLOW_CTRL_REG (0x95 << MEM_MAP_SHIFT)
+#define ADC_SLOW_CTRL_REG (0x43 << MEM_MAP_SHIFT)
 
 #define ADC_SLOW_CTRL_STRT_OFST (0)
 #define ADC_SLOW_CTRL_STRT_MSK  (0x00000001 << ADC_SLOW_CTRL_STRT_OFST)

slsDetectorServers/ctbDetectorServer/slsDetectorFunctionList.c

@@ -15,6 +15,7 @@
 #include "loadPattern.h"
 
 #include <netinet/in.h>
+#include <stdio.h>
 #include <stdlib.h>
 #include <string.h>
 #include <unistd.h> // usleep
@@ -93,6 +94,7 @@ void basictests() {
     LOG(logINFOBLUE, ("********* Chip Test Board Virtual Server *********\n"));
 #else
     LOG(logINFOBLUE, ("************* Chip Test Board Server *************\n"));
+    enableBlackfinAMCExternalAccessExtension();
     initError = defineGPIOpins(initErrorMessage);
     if (initError == FAIL) {
         return;
@@ -438,6 +440,33 @@ uint32_t getDetectorIP() {
     return res;
 }
 
+void enableBlackfinAMCExternalAccessExtension() {
+    unsigned int value;
+    const char *file_path = "/sys/kernel/debug/blackfin/ebiu_amc/EBIU_AMBCTL1";
+
+    FILE *file = fopen(file_path, "r");
+    if (!file) {
+        LOG(logERROR, ("Failed to read EBIU_AMBCTL1\n"));
+        return;
+    }
+    fscanf(file, "%x", &value);
+    fclose(file);
+
+    // enable support for ARDY signal on interface to FPGA
+    // needed to properly translate avalon_mm_waitrequest in the CTB firmware
+    // https://www.analog.com/media/en/dsp-documentation/processor-manuals/bf537_hwr_Rev3.2.pdf
+    // page 274
+    value |= 0x3;
+
+    file = fopen(file_path, "w");
+    if (!file) {
+        LOG(logERROR, ("Failed to enable blackfin AMC access extension\n"));
+        return;
+    }
+    fprintf(file, "0x%x", value);
+    fclose(file);
+}
+
 /* initialization */
 
 void initControlServer() {

slsDetectorServers/slsDetectorServer/include/slsDetectorFunctionList.h

@@ -135,6 +135,7 @@ void setupDetector();
 #if defined(CHIPTESTBOARDD)
 int updateDatabytesandAllocateRAM();
 void updateDataBytes();
+void enableBlackfinAMCExternalAccessExtension();
 #endif
 
 #if !defined(CHIPTESTBOARDD) && !defined(XILINX_CHIPTESTBOARDD)

slsDetectorServers/xilinx_ctbDetectorServer/CMakeLists.txt

@@ -44,5 +44,6 @@ install(TARGETS xilinx_ctbDetectorServer_virtual
 configure_file(chip_config_xilinx.txt ${CMAKE_BINARY_DIR}/bin/chip_config_xilinx.txt COPYONLY)
 configure_file(reset_chip_xilinx.txt ${CMAKE_BINARY_DIR}/bin/reset_chip_xilinx.txt COPYONLY)
 configure_file(enable_clock_pattern.pyat ${CMAKE_BINARY_DIR}/bin/enable_clock_pattern.pyat COPYONLY)
+configure_file(put_trimbits_zero.pyat ${CMAKE_BINARY_DIR}/bin/put_trimbits_zero.pyat COPYONLY)
 configure_file(readout_pattern.pyat ${CMAKE_BINARY_DIR}/bin/readout_pattern.pyat COPYONLY)
 

slsDetectorServers/xilinx_ctbDetectorServer/Makefile

@@ -51,6 +51,7 @@ $(PROGS): $(OBJS)
 	cp chip_config_xilinx.txt $(DESTDIR)
 	cp reset_chip_xilinx.txt $(DESTDIR)
 	cp enable_clock_pattern.pyat $(DESTDIR)
+	cp put_trimbits_zero.pyat $(DESTDIR)
 	cp readout_pattern.pyat $(DESTDIR)
 	rm $(main_src)*.o $(md5_dir)*.o
 clean:

slsDetectorServers/xilinx_ctbDetectorServer/RegisterDefs.h

@@ -2,10 +2,12 @@
 // Copyright (C) 2021 Contributors to the SLS Detector Package
 #pragma once
 
+#define PATTERN_RAM_BASE_ADDR (0x0000)
+
 #define CTRL_REG (0x8000)
 
-#define POWER_VIO_OFST   (0)
-#define POWER_VIO_MSK    (0x00000001 << POWER_VIO_OFST)
+#define POWER_VIO_OFST (0)
+#define POWER_VIO_MSK  (0x00000001 << POWER_VIO_OFST)
 #define POWER_VCC_A_OFST (1)
 #define POWER_VCC_A_MSK  (0x00000001 << POWER_VCC_A_OFST)
 #define POWER_VCC_B_OFST (2)
@@ -17,20 +19,20 @@
 
 #define STATUS_REG (0x8004)
 
-#define PATTERN_RUNNING_OFST  (0)
-#define PATTERN_RUNNING_MSK   (0x00000001 << PATTERN_RUNNING_OFST)
-#define RX_BUSY_OFST          (1)
-#define RX_BUSY_MSK           (0x00000001 << RX_BUSY_OFST)
-#define PROCESSING_BUSY_OFST  (2)
-#define PROCESSING_BUSY_MSK   (0x00000001 << PROCESSING_BUSY_OFST)
-#define UDP_GEN_BUSY_OFST     (3)
-#define UDP_GEN_BUSY_MSK      (0x00000001 << UDP_GEN_BUSY_OFST)
-#define NETWORK_BUSY_OFST     (4)
-#define NETWORK_BUSY_MSK      (0x00000001 << NETWORK_BUSY_OFST)
+#define PATTERN_RUNNING_OFST (0)
+#define PATTERN_RUNNING_MSK  (0x00000001 << PATTERN_RUNNING_OFST)
+#define RX_BUSY_OFST (1)
+#define RX_BUSY_MSK  (0x00000001 << RX_BUSY_OFST)
+#define PROCESSING_BUSY_OFST (2)
+#define PROCESSING_BUSY_MSK  (0x00000001 << PROCESSING_BUSY_OFST)
+#define UDP_GEN_BUSY_OFST (3)
+#define UDP_GEN_BUSY_MSK  (0x00000001 << UDP_GEN_BUSY_OFST)
+#define NETWORK_BUSY_OFST (4)
+#define NETWORK_BUSY_MSK  (0x00000001 << NETWORK_BUSY_OFST)
 #define WAIT_FOR_TRIGGER_OFST (5)
 #define WAIT_FOR_TRIGGER_MSK  (0x00000001 << WAIT_FOR_TRIGGER_OFST)
-#define RX_NOT_GOOD_OFST      (6)
-#define RX_NOT_GOOD_MSK       (0x00000001 << RX_NOT_GOOD_OFST)
+#define RX_NOT_GOOD_OFST (6)
+#define RX_NOT_GOOD_MSK  (0x00000001 << RX_NOT_GOOD_OFST)
 
 #define STATUS_REG2 (0x8008)
 
@@ -38,8 +40,8 @@
 
 #define FPGACOMPDATE_OFST (0)
 #define FPGACOMPDATE_MSK  (0x00ffffff << FPGACOMPDATE_OFST)
-#define FPGADETTYPE_OFST  (24)
-#define FPGADETTYPE_MSK   (0x000000ff << FPGADETTYPE_OFST)
+#define FPGADETTYPE_OFST (24)
+#define FPGADETTYPE_MSK  (0x000000ff << FPGADETTYPE_OFST)
 
 #define FPGA_GIT_HEAD (0x8010)
 
@@ -50,8 +52,8 @@
 
 #define APICOMPDATE_OFST (0)
 #define APICOMPDATE_MSK  (0x00ffffff << APICOMPDATE_OFST)
-#define APIDETTYPE_OFST  (24)
-#define APIDETTYPE_MSK   (0x000000ff << APIDETTYPE_OFST)
+#define APIDETTYPE_OFST (24)
+#define APIDETTYPE_MSK  (0x000000ff << APIDETTYPE_OFST)
 
 #define A_FIFO_OVERFLOW_STATUS_REG (0x9000)
 
@@ -103,23 +105,22 @@
 
 #define FIFO_TO_GB_CONTROL_REG (0xA000)
 
-#define ENABLED_CHANNELS_ADC_OFST     (0)
-#define ENABLED_CHANNELS_ADC_MSK      (0x000000ff << ENABLED_CHANNELS_ADC_OFST)
-#define ENABLED_CHANNELS_D_OFST       (8)
-#define ENABLED_CHANNELS_D_MSK        (0x00000001 << ENABLED_CHANNELS_D_OFST)
-#define ENABLED_CHANNELS_X_OFST       (9)
-#define ENABLED_CHANNELS_X_MSK        (0x0000000f << ENABLED_CHANNELS_X_OFST)
-#define RO_MODE_ADC_OFST              (13)
-#define RO_MODE_ADC_MSK               (0x00000001 << RO_MODE_ADC_OFST)
-#define RO_MODE_D_OFST                (14)
-#define RO_MODE_D_MSK                 (0x00000001 << RO_MODE_D_OFST)
-#define RO_MODE_X_OFST                (15)
-#define RO_MODE_X_MSK                 (0x00000001 << RO_MODE_X_OFST)
+#define ENABLED_CHANNELS_ADC_OFST (0)
+#define ENABLED_CHANNELS_ADC_MSK  (0x000000ff << ENABLED_CHANNELS_ADC_OFST)
+#define ENABLED_CHANNELS_D_OFST (8)
+#define ENABLED_CHANNELS_D_MSK  (0x00000001 << ENABLED_CHANNELS_D_OFST)
+#define ENABLED_CHANNELS_X_OFST (9)
+#define ENABLED_CHANNELS_X_MSK  (0x0000000f << ENABLED_CHANNELS_X_OFST)
+#define RO_MODE_ADC_OFST (13)
+#define RO_MODE_ADC_MSK  (0x00000001 << RO_MODE_ADC_OFST)
+#define RO_MODE_D_OFST (14)
+#define RO_MODE_D_MSK  (0x00000001 << RO_MODE_D_OFST)
+#define RO_MODE_X_OFST (15)
+#define RO_MODE_X_MSK  (0x00000001 << RO_MODE_X_OFST)
 #define COUNT_FRAMES_FROM_UPDATE_OFST (16)
-#define COUNT_FRAMES_FROM_UPDATE_MSK                                           \
-    (0x00000001 << COUNT_FRAMES_FROM_UPDATE_OFST)
-#define START_STREAMING_P_OFST   (17)
-#define START_STREAMING_P_MSK    (0x00000001 << START_STREAMING_P_OFST)
+#define COUNT_FRAMES_FROM_UPDATE_MSK  (0x00000001 << COUNT_FRAMES_FROM_UPDATE_OFST)
+#define START_STREAMING_P_OFST (17)
+#define START_STREAMING_P_MSK  (0x00000001 << START_STREAMING_P_OFST)
 #define STREAM_BUFFER_CLEAR_OFST (18)
 #define STREAM_BUFFER_CLEAR_MSK  (0x00000001 << STREAM_BUFFER_CLEAR_OFST)
 
@@ -148,26 +149,26 @@
 
 #define PKTPACKETLENGTHREG (0xA020)
 
-#define PACKETLENGTH1G_OFST  (0)
-#define PACKETLENGTH1G_MSK   (0x0000ffff << PACKETLENGTH1G_OFST)
+#define PACKETLENGTH1G_OFST (0)
+#define PACKETLENGTH1G_MSK  (0x0000ffff << PACKETLENGTH1G_OFST)
 #define PACKETLENGTH10G_OFST (16)
 #define PACKETLENGTH10G_MSK  (0x0000ffff << PACKETLENGTH10G_OFST)
 
 #define PKTNOPACKETSREG (0xA024)
 
-#define NOPACKETS1G_OFST  (0)
-#define NOPACKETS1G_MSK   (0x0000003f << NOPACKETS1G_OFST)
+#define NOPACKETS1G_OFST (0)
+#define NOPACKETS1G_MSK  (0x0000003f << NOPACKETS1G_OFST)
 #define NOPACKETS10G_OFST (16)
 #define NOPACKETS10G_MSK  (0x0000003f << NOPACKETS10G_OFST)
 
 #define PKTCTRLREG (0xA028)
 
-#define NOSERVERS_OFST   (0)
-#define NOSERVERS_MSK    (0x0000003f << NOSERVERS_OFST)
+#define NOSERVERS_OFST (0)
+#define NOSERVERS_MSK  (0x0000003f << NOSERVERS_OFST)
 #define SERVERSTART_OFST (8)
 #define SERVERSTART_MSK  (0x0000001f << SERVERSTART_OFST)
-#define ETHINTERF_OFST   (16)
-#define ETHINTERF_MSK    (0x00000001 << ETHINTERF_OFST)
+#define ETHINTERF_OFST (16)
+#define ETHINTERF_MSK  (0x00000001 << ETHINTERF_OFST)
 
 #define PKTCOORDREG1 (0xA02C)
 
@@ -181,124 +182,306 @@
 #define COORDZ_OFST (0)
 #define COORDZ_MSK  (0x0000ffff << COORDZ_OFST)
 
-#define FLOW_STATUS_REG (0xB000)
+#define PATTERN_OUT_LSB_REG (0xB000)
 
-#define RSM_BUSY_OFST     (0)
-#define RSM_BUSY_MSK      (0x00000001 << RSM_BUSY_OFST)
-#define RSM_TRG_WAIT_OFST (3)
-#define RSM_TRG_WAIT_MSK  (0x00000001 << RSM_TRG_WAIT_OFST)
-#define CSM_BUSY_OFST     (17)
-#define CSM_BUSY_MSK      (0x00000001 << CSM_BUSY_OFST)
+#define PATTERN_OUT_MSB_REG (0xB004)
 
-#define FLOW_CONTROL_REG (0xB004)
+#define PATTERN_IN_LSB_REG (0xB008)
 
-#define START_F_OFST        (0)
-#define START_F_MSK         (0x00000001 << START_F_OFST)
-#define STOP_F_OFST         (1)
-#define STOP_F_MSK          (0x00000001 << STOP_F_OFST)
-#define RST_F_OFST          (2)
-#define RST_F_MSK           (0x00000001 << RST_F_OFST)
-#define SW_TRIGGER_F_OFST   (3)
-#define SW_TRIGGER_F_MSK    (0x00000001 << SW_TRIGGER_F_OFST)
-#define TRIGGER_ENABLE_OFST (4)
-#define TRIGGER_ENABLE_MSK  (0x00000001 << TRIGGER_ENABLE_OFST)
+#define PATTERN_IN_MSB_REG (0xB00C)
 
-#define TIME_FROM_START_OUT_REG_1 (0xB008)
+#define PATTERN_MASK_LSB_REG (0xB010)
 
-#define TIME_FROM_START_OUT_REG_2 (0xB00C)
+#define PATTERN_MASK_MSB_REG (0xB014)
 
-#define FRAMES_FROM_START_OUT_REG_1 (0xB010)
+#define PATTERN_SET_LSB_REG (0xB018)
 
-#define FRAMES_FROM_START_OUT_REG_2 (0xB014)
+#define PATTERN_SET_MSB_REG (0xB01C)
 
-#define FRAME_TIME_OUT_REG_1 (0xB018)
+#define PATTERN_CNTRL_REG (0xB020)
 
-#define FRAME_TIME_OUT_REG_2 (0xB01C)
-
-#define DELAY_OUT_REG_1 (0xB020)
-
-#define DELAY_OUT_REG_2 (0xB024)
-
-#define CYCLES_OUT_REG_1 (0xB028)
-
-#define CYCLES_OUT_REG_2 (0xB02C)
-
-#define FRAMES_OUT_REG_1 (0xB030)
-
-#define FRAMES_OUT_REG_2 (0xB034)
-
-#define PERIOD_OUT_REG_1 (0xB038)
-
-#define PERIOD_OUT_REG_2 (0xB03C)
-
-#define DELAY_IN_REG_1 (0xB040)
-
-#define DELAY_IN_REG_2 (0xB044)
-
-#define CYCLES_IN_REG_1 (0xB048)
-
-#define CYCLES_IN_REG_2 (0xB04C)
-
-#define FRAMES_IN_REG_1 (0xB050)
-
-#define FRAMES_IN_REG_2 (0xB054)
-
-#define PERIOD_IN_REG_1 (0xB058)
-
-#define PERIOD_IN_REG_2 (0xB05C)
-
-#define PATTERN_OUT_LSB_REG (0xB100)
-
-#define PATTERN_OUT_MSB_REG (0xB104)
-
-#define PATTERN_IN_LSB_REG (0xB108)
-
-#define PATTERN_IN_MSB_REG (0xB10C)
-
-#define PATTERN_MASK_LSB_REG (0xB110)
-
-#define PATTERN_MASK_MSB_REG (0xB114)
-
-#define PATTERN_SET_LSB_REG (0xB118)
-
-#define PATTERN_SET_MSB_REG (0xB11C)
-
-#define PATTERN_CNTRL_REG (0xB120)
-
-#define PATTERN_CNTRL_WR_OFST   (0)
-#define PATTERN_CNTRL_WR_MSK    (0x00000001 << PATTERN_CNTRL_WR_OFST)
-#define PATTERN_CNTRL_RD_OFST   (1)
-#define PATTERN_CNTRL_RD_MSK    (0x00000001 << PATTERN_CNTRL_RD_OFST)
+#define PATTERN_CNTRL_WR_OFST (0)
+#define PATTERN_CNTRL_WR_MSK  (0x00000001 << PATTERN_CNTRL_WR_OFST)
+#define PATTERN_CNTRL_RD_OFST (1)
+#define PATTERN_CNTRL_RD_MSK  (0x00000001 << PATTERN_CNTRL_RD_OFST)
 #define PATTERN_CNTRL_ADDR_OFST (16)
 #define PATTERN_CNTRL_ADDR_MSK  (0x00001fff << PATTERN_CNTRL_ADDR_OFST)
 
-#define PATTERN_LIMIT_REG (0xB124)
+#define PATTERN_LIMIT_REG (0xB024)
 
 #define PATTERN_LIMIT_STRT_OFST (0)
 #define PATTERN_LIMIT_STRT_MSK  (0x00001fff << PATTERN_LIMIT_STRT_OFST)
-#define PATTERN_LIMIT_STP_OFST  (16)
-#define PATTERN_LIMIT_STP_MSK   (0x00001fff << PATTERN_LIMIT_STP_OFST)
+#define PATTERN_LIMIT_STP_OFST (16)
+#define PATTERN_LIMIT_STP_MSK  (0x00001fff << PATTERN_LIMIT_STP_OFST)
 
-#define PATTERN_LOOP_0_ADDR_REG (0xB128)
+#define PATTERN_IO_CNTRL_LSB_REG (0xB028)
 
+#define PATTERN_IO_CNTRL_MSB_REG (0xB02C)
+
+#define FLOW_CONTROL_REG (0xB030)
+
+#define START_F_OFST (0)
+#define START_F_MSK  (0x00000001 << START_F_OFST)
+#define STOP_F_OFST (1)
+#define STOP_F_MSK  (0x00000001 << STOP_F_OFST)
+#define RST_F_OFST (2)
+#define RST_F_MSK  (0x00000001 << RST_F_OFST)
+#define SW_TRIGGER_F_OFST (3)
+#define SW_TRIGGER_F_MSK  (0x00000001 << SW_TRIGGER_F_OFST)
+#define TRIGGER_ENABLE_OFST (4)
+#define TRIGGER_ENABLE_MSK  (0x00000001 << TRIGGER_ENABLE_OFST)
+#define RSM_BUSY_OFST (5)
+#define RSM_BUSY_MSK  (0x00000001 << RSM_BUSY_OFST)
+#define RSM_TRG_WAIT_OFST (6)
+#define RSM_TRG_WAIT_MSK  (0x00000001 << RSM_TRG_WAIT_OFST)
+#define CSM_BUSY_OFST (7)
+#define CSM_BUSY_MSK  (0x00000001 << CSM_BUSY_OFST)
+
+#define DELAY_IN_REG_1 (0xB034)
+
+#define DELAY_IN_REG_2 (0xB038)
+
+#define CYCLES_IN_REG_1 (0xB03C)
+
+#define CYCLES_IN_REG_2 (0xB040)
+
+#define FRAMES_IN_REG_1 (0xB044)
+
+#define FRAMES_IN_REG_2 (0xB048)
+
+#define PERIOD_IN_REG_1 (0xB04C)
+
+#define PERIOD_IN_REG_2 (0xB050)
+
+#define DELAY_OUT_REG_1 (0xB054)
+
+#define DELAY_OUT_REG_2 (0xB058)
+
+#define CYCLES_OUT_REG_1 (0xB05C)
+
+#define CYCLES_OUT_REG_2 (0xB060)
+
+#define FRAMES_OUT_REG_1 (0xB064)
+
+#define FRAMES_OUT_REG_2 (0xB068)
+
+#define PERIOD_OUT_REG_1 (0xB06C)
+
+#define PERIOD_OUT_REG_2 (0xB070)
+
+#define PATTERN_TEST_REG (0xB074)
+
+#define PATTERN_FIRMWARE_REG (0xB078)
+
+#define PATTERN_WIDTH_OFST (0)
+#define PATTERN_WIDTH_MSK  (0x000000ff << PATTERN_WIDTH_OFST)
+#define PATTERN_ADDR_WIDTH_OFST (8)
+#define PATTERN_ADDR_WIDTH_MSK  (0x000000ff << PATTERN_ADDR_WIDTH_OFST)
+#define PATTERN_NLOOPS_NWAITS_OFST (16)
+#define PATTERN_NLOOPS_NWAITS_MSK  (0x000000ff << PATTERN_NLOOPS_NWAITS_OFST)
+#define DIRECT_PATTERN_RAM_OFST (24)
+#define DIRECT_PATTERN_RAM_MSK  (0x00000001 << DIRECT_PATTERN_RAM_OFST)
+
+#define TIME_FROM_START_OUT_REG_1 (0xB07C)
+
+#define TIME_FROM_START_OUT_REG_2 (0xB080)
+
+#define FRAMES_FROM_START_OUT_REG_1 (0xB084)
+
+#define FRAMES_FROM_START_OUT_REG_2 (0xB088)
+
+#define FRAME_TIME_OUT_REG_1 (0xB08C)
+
+#define FRAME_TIME_OUT_REG_2 (0xB090)
+
+#define PATTERN_LOOPDEF_START_REG (0xB080)
+
+#define PATTERN_LOOPDEF_LOOP_ADDR_OFST (0)
+#define PATTERN_LOOPDEF_LOOP_ADDR_MSK  (0x00000001 << PATTERN_LOOPDEF_LOOP_ADDR_OFST)
+#define PATTERN_LOOPDEF_LOOP_ITERATION_OFST (1)
+#define PATTERN_LOOPDEF_LOOP_ITERATION_MSK  (0x00000001 << PATTERN_LOOPDEF_LOOP_ITERATION_OFST)
+#define PATTERN_LOOPDEF_WAIT_ADDR_OFST (2)
+#define PATTERN_LOOPDEF_WAIT_ADDR_MSK  (0x00000001 << PATTERN_LOOPDEF_WAIT_ADDR_OFST)
+#define PATTERN_LOOPDEF_WAIT_TIME_LSB_OFST (3)
+#define PATTERN_LOOPDEF_WAIT_TIME_LSB_MSK  (0x00000001 << PATTERN_LOOPDEF_WAIT_TIME_LSB_OFST)
+#define PATTERN_LOOPDEF_WAIT_TIME_MSB_OFST (4)
+#define PATTERN_LOOPDEF_WAIT_TIME_MSB_MSK  (0x00000001 << PATTERN_LOOPDEF_WAIT_TIME_MSB_OFST)
+
+#define DBITFIFOCTRLREG (0xC000)
+
+#define DBITRD_OFST (0)
+#define DBITRD_MSK  (0x00000001 << DBITRD_OFST)
+#define DBITRST_OFST (1)
+#define DBITRST_MSK  (0x00000001 << DBITRST_OFST)
+#define DBITFULL_OFST (2)
+#define DBITFULL_MSK  (0x00000001 << DBITFULL_OFST)
+#define DBITEMPTY_OFST (3)
+#define DBITEMPTY_MSK  (0x00000001 << DBITEMPTY_OFST)
+#define DBITUNDERFLOW_OFST (4)
+#define DBITUNDERFLOW_MSK  (0x00000001 << DBITUNDERFLOW_OFST)
+#define DBITOVERFLOW_OFST (5)
+#define DBITOVERFLOW_MSK  (0x00000001 << DBITOVERFLOW_OFST)
+
+#define DBITFIFODATAREG1 (0xC004)
+
+#define DBITFIFODATAREG2 (0xC008)
+
+#define MATTERHORNSPIREG1 (0xC00C)
+
+#define MATTERHORNSPIREG2 (0xC010)
+
+#define MATTERHORNSPICTRL (0xC014)
+
+#define CONFIGSTART_P_OFST (0)
+#define CONFIGSTART_P_MSK  (0x00000001 << CONFIGSTART_P_OFST)
+#define PERIPHERYRST_P_OFST (1)
+#define PERIPHERYRST_P_MSK  (0x00000001 << PERIPHERYRST_P_OFST)
+#define STARTREAD_P_OFST (2)
+#define STARTREAD_P_MSK  (0x00000001 << STARTREAD_P_OFST)
+#define BUSY_OFST (3)
+#define BUSY_MSK  (0x00000001 << BUSY_OFST)
+#define READOUTFROMASIC_OFST (4)
+#define READOUTFROMASIC_MSK  (0x00000001 << READOUTFROMASIC_OFST)
+
+#define TRANSCEIVERRXCTRL0REG1 (0xC100)
+
+#define TRANSCEIVERRXCTRL0REG2 (0xC104)
+
+#define TRANSCEIVERRXCTRL1REG1 (0xC108)
+
+#define TRANSCEIVERRXCTRL1REG2 (0xC10C)
+
+#define TRANSCEIVERRXCTRL2REG (0xC110)
+
+#define TRANSCEIVERRXCTRL3REG (0xC114)
+
+#define TRANSCEIVERSTATUS (0xC118)
+
+#define LINKDOWNLATCHEDOUT_OFST (0)
+#define LINKDOWNLATCHEDOUT_MSK  (0x00000001 << LINKDOWNLATCHEDOUT_OFST)
+#define TXUSERCLKACTIVE_OFST (1)
+#define TXUSERCLKACTIVE_MSK  (0x00000001 << TXUSERCLKACTIVE_OFST)
+#define RXUSERCLKACTIVE_OFST (2)
+#define RXUSERCLKACTIVE_MSK  (0x00000001 << RXUSERCLKACTIVE_OFST)
+#define RXCOMMADET_OFST (3)
+#define RXCOMMADET_MSK  (0x0000000f << RXCOMMADET_OFST)
+#define RXBYTEREALIGN_OFST (7)
+#define RXBYTEREALIGN_MSK  (0x0000000f << RXBYTEREALIGN_OFST)
+#define RXBYTEISALIGNED_OFST (11)
+#define RXBYTEISALIGNED_MSK  (0x0000000f << RXBYTEISALIGNED_OFST)
+#define GTWIZRXCDRSTABLE_OFST (15)
+#define GTWIZRXCDRSTABLE_MSK  (0x00000001 << GTWIZRXCDRSTABLE_OFST)
+#define RESETTXDONE_OFST (16)
+#define RESETTXDONE_MSK  (0x00000001 << RESETTXDONE_OFST)
+#define RESETRXDONE_OFST (17)
+#define RESETRXDONE_MSK  (0x00000001 << RESETRXDONE_OFST)
+#define RXPMARESETDONE_OFST (18)
+#define RXPMARESETDONE_MSK  (0x0000000f << RXPMARESETDONE_OFST)
+#define TXPMARESETDONE_OFST (22)
+#define TXPMARESETDONE_MSK  (0x0000000f << TXPMARESETDONE_OFST)
+#define GTTPOWERGOOD_OFST (26)
+#define GTTPOWERGOOD_MSK  (0x0000000f << GTTPOWERGOOD_OFST)
+
+#define TRANSCEIVERSTATUS2 (0xC11C)
+
+#define RXLOCKED_OFST (0)
+#define RXLOCKED_MSK  (0x0000000f << RXLOCKED_OFST)
+
+#define TRANSCEIVERCONTROL (0xC120)
+
+#define GTWIZRESETALL_OFST (0)
+#define GTWIZRESETALL_MSK  (0x00000001 << GTWIZRESETALL_OFST)
+#define RESETTXPLLANDDATAPATH_OFST (1)
+#define RESETTXPLLANDDATAPATH_MSK  (0x00000001 << RESETTXPLLANDDATAPATH_OFST)
+#define RESETTXDATAPATHIN_OFST (2)
+#define RESETTXDATAPATHIN_MSK  (0x00000001 << RESETTXDATAPATHIN_OFST)
+#define RESETRXPLLANDDATAPATH_OFST (3)
+#define RESETRXPLLANDDATAPATH_MSK  (0x00000001 << RESETRXPLLANDDATAPATH_OFST)
+#define RESETRXDATAPATHIN_OFST (4)
+#define RESETRXDATAPATHIN_MSK  (0x00000001 << RESETRXDATAPATHIN_OFST)
+#define RXPOLARITY_OFST (5)
+#define RXPOLARITY_MSK  (0x0000000f << RXPOLARITY_OFST)
+#define RXERRORCNTRESET_OFST (9)
+#define RXERRORCNTRESET_MSK  (0x0000000f << RXERRORCNTRESET_OFST)
+#define RXMSBLSBINVERT_OFST (13)
+#define RXMSBLSBINVERT_MSK  (0x0000000f << RXMSBLSBINVERT_OFST)
+
+#define TRANSCEIVERERRCNT_REG0 (0xC124)
+
+#define TRANSCEIVERERRCNT_REG1 (0xC128)
+
+#define TRANSCEIVERERRCNT_REG2 (0xC12C)
+
+#define TRANSCEIVERERRCNT_REG3 (0xC130)
+
+#define TRANSCEIVERALIGNCNT_REG0 (0xC134)
+
+#define RXALIGNCNTCH0_OFST (0)
+#define RXALIGNCNTCH0_MSK  (0x0000ffff << RXALIGNCNTCH0_OFST)
+
+#define TRANSCEIVERALIGNCNT_REG1 (0xC138)
+
+#define RXALIGNCNTCH1_OFST (0)
+#define RXALIGNCNTCH1_MSK  (0x0000ffff << RXALIGNCNTCH1_OFST)
+
+#define TRANSCEIVERALIGNCNT_REG2 (0xC13C)
+
+#define RXALIGNCNTCH2_OFST (0)
+#define RXALIGNCNTCH2_MSK  (0x0000ffff << RXALIGNCNTCH2_OFST)
+
+#define TRANSCEIVERALIGNCNT_REG3 (0xC140)
+
+#define RXALIGNCNTCH3_OFST (0)
+#define RXALIGNCNTCH3_MSK  (0x0000ffff << RXALIGNCNTCH3_OFST)
+
+#define TRANSCEIVERLASTWORD_REG0 (0xC144)
+
+#define RXDATACH0_OFST (0)
+#define RXDATACH0_MSK  (0x0000ffff << RXDATACH0_OFST)
+
+#define TRANSCEIVERLASTWORD_REG1 (0xC148)
+
+#define RXDATACH1_OFST (0)
+#define RXDATACH1_MSK  (0x0000ffff << RXDATACH1_OFST)
+
+#define TRANSCEIVERLASTWORD_REG2 (0xC14C)
+
+#define RXDATACH2_OFST (0)
+#define RXDATACH2_MSK  (0x0000ffff << RXDATACH2_OFST)
+
+#define TRANSCEIVERLASTWORD_REG3 (0xC150)
+
+#define RXDATACH3_OFST (0)
+#define RXDATACH3_MSK  (0x0000ffff << RXDATACH3_OFST)
+
+
+
+
+// ----------------------------------------------------
+// TODO: remove these:
+
+
+//-----------------------------------
+#define PINIOCTRLREG (0xB028)
+
+#define PATTERN_LOOP_0_ADDR_REG (0xB080)
 #define PATTERN_LOOP_0_ADDR_STRT_OFST (0)
 #define PATTERN_LOOP_0_ADDR_STRT_MSK                                           \
     (0x00001fff << PATTERN_LOOP_0_ADDR_STRT_OFST)
 #define PATTERN_LOOP_0_ADDR_STP_OFST (16)
 #define PATTERN_LOOP_0_ADDR_STP_MSK  (0x00001fff << PATTERN_LOOP_0_ADDR_STP_OFST)
+#define PATTERN_LOOP_0_ITERATION_REG (0xB084)
 
-#define PATTERN_LOOP_0_ITERATION_REG (0xB12C)
-
-#define PATTERN_WAIT_0_ADDR_REG (0xB130)
+#define PATTERN_WAIT_0_ADDR_REG (0xB088)
 
 #define PATTERN_WAIT_0_ADDR_OFST (0)
 #define PATTERN_WAIT_0_ADDR_MSK  (0x00001fff << PATTERN_WAIT_0_ADDR_OFST)
 
-#define PATTERN_WAIT_TIMER_0_LSB_REG (0xB134)
+#define PATTERN_WAIT_TIMER_0_LSB_REG (0xB08C)
 
-#define PATTERN_WAIT_TIMER_0_MSB_REG (0xB138)
+#define PATTERN_WAIT_TIMER_0_MSB_REG (0xB090)
 
-#define PATTERN_LOOP_1_ADDR_REG (0xB13C)
+#define PATTERN_LOOP_1_ADDR_REG (0xB094)
 
 #define PATTERN_LOOP_1_ADDR_STRT_OFST (0)
 #define PATTERN_LOOP_1_ADDR_STRT_MSK                                           \
@@ -306,18 +489,18 @@
 #define PATTERN_LOOP_1_ADDR_STP_OFST (16)
 #define PATTERN_LOOP_1_ADDR_STP_MSK  (0x00001fff << PATTERN_LOOP_1_ADDR_STP_OFST)
 
-#define PATTERN_LOOP_1_ITERATION_REG (0xB140)
+#define PATTERN_LOOP_1_ITERATION_REG (0xB098)
 
-#define PATTERN_WAIT_1_ADDR_REG (0xB144)
+#define PATTERN_WAIT_1_ADDR_REG (0xB09C)
 
 #define PATTERN_WAIT_1_ADDR_OFST (0)
 #define PATTERN_WAIT_1_ADDR_MSK  (0x00001fff << PATTERN_WAIT_1_ADDR_OFST)
 
-#define PATTERN_WAIT_TIMER_1_LSB_REG (0xB148)
+#define PATTERN_WAIT_TIMER_1_LSB_REG (0xB0A0)
 
-#define PATTERN_WAIT_TIMER_1_MSB_REG (0xB14C)
+#define PATTERN_WAIT_TIMER_1_MSB_REG (0xB0A4)
 
-#define PATTERN_LOOP_2_ADDR_REG (0xB150)
+#define PATTERN_LOOP_2_ADDR_REG (0xB0A8)
 
 #define PATTERN_LOOP_2_ADDR_STRT_OFST (0)
 #define PATTERN_LOOP_2_ADDR_STRT_MSK                                           \
@@ -325,18 +508,18 @@
 #define PATTERN_LOOP_2_ADDR_STP_OFST (16)
 #define PATTERN_LOOP_2_ADDR_STP_MSK  (0x00001fff << PATTERN_LOOP_2_ADDR_STP_OFST)
 
-#define PATTERN_LOOP_2_ITERATION_REG (0xB154)
+#define PATTERN_LOOP_2_ITERATION_REG (0xB0AC)
 
-#define PATTERN_WAIT_2_ADDR_REG (0xB158)
+#define PATTERN_WAIT_2_ADDR_REG (0xB0B0)
 
 #define PATTERN_WAIT_2_ADDR_OFST (0)
 #define PATTERN_WAIT_2_ADDR_MSK  (0x00001fff << PATTERN_WAIT_2_ADDR_OFST)
 
-#define PATTERN_WAIT_TIMER_2_LSB_REG (0xB15C)
+#define PATTERN_WAIT_TIMER_2_LSB_REG (0xB0B4)
 
-#define PATTERN_WAIT_TIMER_2_MSB_REG (0xB160)
+#define PATTERN_WAIT_TIMER_2_MSB_REG (0xB0B8)
 
-#define PATTERN_LOOP_3_ADDR_REG (0xB164)
+#define PATTERN_LOOP_3_ADDR_REG (0xB0BC)
 
 #define PATTERN_LOOP_3_ADDR_STRT_OFST (0)
 #define PATTERN_LOOP_3_ADDR_STRT_MSK                                           \
@@ -344,18 +527,18 @@
 #define PATTERN_LOOP_3_ADDR_STP_OFST (16)
 #define PATTERN_LOOP_3_ADDR_STP_MSK  (0x00001fff << PATTERN_LOOP_3_ADDR_STP_OFST)
 
-#define PATTERN_LOOP_3_ITERATION_REG (0xB168)
+#define PATTERN_LOOP_3_ITERATION_REG (0xB0C0)
 
-#define PATTERN_WAIT_3_ADDR_REG (0xB16C)
+#define PATTERN_WAIT_3_ADDR_REG (0xB0C4)
 
 #define PATTERN_WAIT_3_ADDR_OFST (0)
 #define PATTERN_WAIT_3_ADDR_MSK  (0x00001fff << PATTERN_WAIT_3_ADDR_OFST)
 
-#define PATTERN_WAIT_TIMER_3_LSB_REG (0xB170)
+#define PATTERN_WAIT_TIMER_3_LSB_REG (0xB0C8)
 
-#define PATTERN_WAIT_TIMER_3_MSB_REG (0xB174)
+#define PATTERN_WAIT_TIMER_3_MSB_REG (0xB0CC)
 
-#define PATTERN_LOOP_4_ADDR_REG (0xB178)
+#define PATTERN_LOOP_4_ADDR_REG (0xB0D0)
 
 #define PATTERN_LOOP_4_ADDR_STRT_OFST (0)
 #define PATTERN_LOOP_4_ADDR_STRT_MSK                                           \
@@ -363,18 +546,18 @@
 #define PATTERN_LOOP_4_ADDR_STP_OFST (16)
 #define PATTERN_LOOP_4_ADDR_STP_MSK  (0x00001fff << PATTERN_LOOP_4_ADDR_STP_OFST)
 
-#define PATTERN_LOOP_4_ITERATION_REG (0xB17C)
+#define PATTERN_LOOP_4_ITERATION_REG (0xB0D4)
 
-#define PATTERN_WAIT_4_ADDR_REG (0xB180)
+#define PATTERN_WAIT_4_ADDR_REG (0xB0D8)
 
 #define PATTERN_WAIT_4_ADDR_OFST (0)
 #define PATTERN_WAIT_4_ADDR_MSK  (0x00001fff << PATTERN_WAIT_4_ADDR_OFST)
 
-#define PATTERN_WAIT_TIMER_4_LSB_REG (0xB184)
+#define PATTERN_WAIT_TIMER_4_LSB_REG (0xB0DC)
 
-#define PATTERN_WAIT_TIMER_4_MSB_REG (0xB188)
+#define PATTERN_WAIT_TIMER_4_MSB_REG (0xB0E0)
 
-#define PATTERN_LOOP_5_ADDR_REG (0xB18C)
+#define PATTERN_LOOP_5_ADDR_REG (0xB0E4)
 
 #define PATTERN_LOOP_5_ADDR_STRT_OFST (0)
 #define PATTERN_LOOP_5_ADDR_STRT_MSK                                           \
@@ -382,162 +565,10 @@
 #define PATTERN_LOOP_5_ADDR_STP_OFST (16)
 #define PATTERN_LOOP_5_ADDR_STP_MSK  (0x00001fff << PATTERN_LOOP_5_ADDR_STP_OFST)
 
-#define PATTERN_LOOP_5_ITERATION_REG (0xB190)
-
-#define PATTERN_WAIT_5_ADDR_REG (0xB194)
+#define PATTERN_LOOP_5_ITERATION_REG (0xB0E8)
 
+#define PATTERN_WAIT_5_ADDR_REG (0xB0EC)
 #define PATTERN_WAIT_5_ADDR_OFST (0)
 #define PATTERN_WAIT_5_ADDR_MSK  (0x00001fff << PATTERN_WAIT_5_ADDR_OFST)
-
-#define PATTERN_WAIT_TIMER_5_LSB_REG (0xB198)
-
-#define PATTERN_WAIT_TIMER_5_MSB_REG (0xB19C)
-
-#define PINIOCTRLREG (0xB1A0)
-
-#define DBITFIFOCTRLREG (0xB1A4)
-
-#define DBITRD_OFST        (0)
-#define DBITRD_MSK         (0x00000001 << DBITRD_OFST)
-#define DBITRST_OFST       (1)
-#define DBITRST_MSK        (0x00000001 << DBITRST_OFST)
-#define DBITFULL_OFST      (2)
-#define DBITFULL_MSK       (0x00000001 << DBITFULL_OFST)
-#define DBITEMPTY_OFST     (3)
-#define DBITEMPTY_MSK      (0x00000001 << DBITEMPTY_OFST)
-#define DBITUNDERFLOW_OFST (4)
-#define DBITUNDERFLOW_MSK  (0x00000001 << DBITUNDERFLOW_OFST)
-#define DBITOVERFLOW_OFST  (5)
-#define DBITOVERFLOW_MSK   (0x00000001 << DBITOVERFLOW_OFST)
-
-#define DBITFIFODATAREG1 (0xB1A8)
-
-#define DBITFIFODATAREG2 (0xB1AC)
-
-#define MATTERHORNSPIREG1 (0xB1B0)
-
-#define MATTERHORNSPIREG2 (0xB1B4)
-
-#define MATTERHORNSPICTRL (0xB1B8)
-
-#define CONFIGSTART_P_OFST   (0)
-#define CONFIGSTART_P_MSK    (0x00000001 << CONFIGSTART_P_OFST)
-#define PERIPHERYRST_P_OFST  (1)
-#define PERIPHERYRST_P_MSK   (0x00000001 << PERIPHERYRST_P_OFST)
-#define STARTREAD_P_OFST     (2)
-#define STARTREAD_P_MSK      (0x00000001 << STARTREAD_P_OFST)
-#define BUSY_OFST            (3)
-#define BUSY_MSK             (0x00000001 << BUSY_OFST)
-#define READOUTFROMASIC_OFST (4)
-#define READOUTFROMASIC_MSK  (0x00000001 << READOUTFROMASIC_OFST)
-
-#define TRANSCEIVERRXCTRL0REG1 (0xB800)
-
-#define TRANSCEIVERRXCTRL0REG2 (0xB804)
-
-#define TRANSCEIVERRXCTRL1REG1 (0xB808)
-
-#define TRANSCEIVERRXCTRL1REG2 (0xB80C)
-
-#define TRANSCEIVERRXCTRL2REG (0xB810)
-
-#define TRANSCEIVERRXCTRL3REG (0xB814)
-
-#define TRANSCEIVERSTATUS (0xB818)
-
-#define LINKDOWNLATCHEDOUT_OFST (0)
-#define LINKDOWNLATCHEDOUT_MSK  (0x00000001 << LINKDOWNLATCHEDOUT_OFST)
-#define TXUSERCLKACTIVE_OFST    (1)
-#define TXUSERCLKACTIVE_MSK     (0x00000001 << TXUSERCLKACTIVE_OFST)
-#define RXUSERCLKACTIVE_OFST    (2)
-#define RXUSERCLKACTIVE_MSK     (0x00000001 << RXUSERCLKACTIVE_OFST)
-#define RXCOMMADET_OFST         (3)
-#define RXCOMMADET_MSK          (0x0000000f << RXCOMMADET_OFST)
-#define RXBYTEREALIGN_OFST      (7)
-#define RXBYTEREALIGN_MSK       (0x0000000f << RXBYTEREALIGN_OFST)
-#define RXBYTEISALIGNED_OFST    (11)
-#define RXBYTEISALIGNED_MSK     (0x0000000f << RXBYTEISALIGNED_OFST)
-#define GTWIZRXCDRSTABLE_OFST   (15)
-#define GTWIZRXCDRSTABLE_MSK    (0x00000001 << GTWIZRXCDRSTABLE_OFST)
-#define RESETTXDONE_OFST        (16)
-#define RESETTXDONE_MSK         (0x00000001 << RESETTXDONE_OFST)
-#define RESETRXDONE_OFST        (17)
-#define RESETRXDONE_MSK         (0x00000001 << RESETRXDONE_OFST)
-#define RXPMARESETDONE_OFST     (18)
-#define RXPMARESETDONE_MSK      (0x0000000f << RXPMARESETDONE_OFST)
-#define TXPMARESETDONE_OFST     (22)
-#define TXPMARESETDONE_MSK      (0x0000000f << TXPMARESETDONE_OFST)
-#define GTTPOWERGOOD_OFST       (26)
-#define GTTPOWERGOOD_MSK        (0x0000000f << GTTPOWERGOOD_OFST)
-
-#define TRANSCEIVERSTATUS2 (0xB81C)
-
-#define RXLOCKED_OFST (0)
-#define RXLOCKED_MSK  (0x0000000f << RXLOCKED_OFST)
-
-#define TRANSCEIVERCONTROL (0xB820)
-
-#define GTWIZRESETALL_OFST         (0)
-#define GTWIZRESETALL_MSK          (0x00000001 << GTWIZRESETALL_OFST)
-#define RESETTXPLLANDDATAPATH_OFST (1)
-#define RESETTXPLLANDDATAPATH_MSK  (0x00000001 << RESETTXPLLANDDATAPATH_OFST)
-#define RESETTXDATAPATHIN_OFST     (2)
-#define RESETTXDATAPATHIN_MSK      (0x00000001 << RESETTXDATAPATHIN_OFST)
-#define RESETRXPLLANDDATAPATH_OFST (3)
-#define RESETRXPLLANDDATAPATH_MSK  (0x00000001 << RESETRXPLLANDDATAPATH_OFST)
-#define RESETRXDATAPATHIN_OFST     (4)
-#define RESETRXDATAPATHIN_MSK      (0x00000001 << RESETRXDATAPATHIN_OFST)
-#define RXPOLARITY_OFST            (5)
-#define RXPOLARITY_MSK             (0x0000000f << RXPOLARITY_OFST)
-#define RXERRORCNTRESET_OFST       (9)
-#define RXERRORCNTRESET_MSK        (0x0000000f << RXERRORCNTRESET_OFST)
-#define RXMSBLSBINVERT_OFST        (13)
-#define RXMSBLSBINVERT_MSK         (0x0000000f << RXMSBLSBINVERT_OFST)
-
-#define TRANSCEIVERERRCNT_REG0 (0xB824)
-
-#define TRANSCEIVERERRCNT_REG1 (0xB828)
-
-#define TRANSCEIVERERRCNT_REG2 (0xB82C)
-
-#define TRANSCEIVERERRCNT_REG3 (0xB830)
-
-#define TRANSCEIVERALIGNCNT_REG0 (0xB834)
-
-#define RXALIGNCNTCH0_OFST (0)
-#define RXALIGNCNTCH0_MSK  (0x0000ffff << RXALIGNCNTCH0_OFST)
-
-#define TRANSCEIVERALIGNCNT_REG1 (0xB838)
-
-#define RXALIGNCNTCH1_OFST (0)
-#define RXALIGNCNTCH1_MSK  (0x0000ffff << RXALIGNCNTCH1_OFST)
-
-#define TRANSCEIVERALIGNCNT_REG2 (0xB83C)
-
-#define RXALIGNCNTCH2_OFST (0)
-#define RXALIGNCNTCH2_MSK  (0x0000ffff << RXALIGNCNTCH2_OFST)
-
-#define TRANSCEIVERALIGNCNT_REG3 (0xB840)
-
-#define RXALIGNCNTCH3_OFST (0)
-#define RXALIGNCNTCH3_MSK  (0x0000ffff << RXALIGNCNTCH3_OFST)
-
-#define TRANSCEIVERLASTWORD_REG0 (0xB844)
-
-#define RXDATACH0_OFST (0)
-#define RXDATACH0_MSK  (0x0000ffff << RXDATACH0_OFST)
-
-#define TRANSCEIVERLASTWORD_REG1 (0xB848)
-
-#define RXDATACH1_OFST (0)
-#define RXDATACH1_MSK  (0x0000ffff << RXDATACH1_OFST)
-
-#define TRANSCEIVERLASTWORD_REG2 (0xB84C)
-
-#define RXDATACH2_OFST (0)
-#define RXDATACH2_MSK  (0x0000ffff << RXDATACH2_OFST)
-
-#define TRANSCEIVERLASTWORD_REG3 (0xB850)
-
-#define RXDATACH3_OFST (0)
-#define RXDATACH3_MSK  (0x0000ffff << RXDATACH3_OFST)
+#define PATTERN_WAIT_TIMER_5_LSB_REG (0xB0F0)
+#define PATTERN_WAIT_TIMER_5_MSB_REG (0xB0F4)

slsDetectorServers/xilinx_ctbDetectorServer/chip_config_xilinx.txt

@@ -1,24 +1,37 @@
 # Prepare MH02 configuration
-reg 0xB1B0 0x00000041
-reg 0xB1B4 0x01200004
+reg 0xC00C 0x00000041
+reg 0xC010 0x01200004
+
+# turn on external CLKSEL for trimbit upload
+setbit 0xC00C 17
 
 # configure Matterhorn SPI
-setbit 0xB1B8 0
+setbit 0xC014 0
 
 # wait till config is done
-pollbit 0xB1B8 3 0
+pollbit 0xC014 3 0
+
+# set trimbits to 0
+pattern put_trimbits_zero.pyat
+setbit 0xB030 0
+clearbit 0xB030 0
+sleep 1
+pollbit 0xB004 0 0
+clearbit 0xC00C 17
+setbit 0xC014 0
+pollbit 0xC014 3 0
 
 # reset transceiver
-reg 0xB820 0x0
-reg 0xB820 0x1
-reg 0xB820 0x0
+reg 0xC120 0x0
+reg 0xC120 0x1
+reg 0xC120 0x0
 
 # set MSB LSB inversions and polarity for transceiver
-reg 0xB820 0x61e0
+reg 0xC120 0x61e0
 
 # Enable MH02 PLL clock
 pattern enable_clock_pattern.pyat
 # start the flow
-setbit 0xB004 0
-clearbit 0xB004 0
+setbit 0xB030 0
+clearbit 0xB030 0
 sleep 1

slsDetectorServers/xilinx_ctbDetectorServer/put_trimbits_zero.pyat

@@ -0,0 +1,82 @@
+patword 0x0000 0x0000000000000000
+patword 0x0001 0x0000000000000000
+patword 0x0002 0x0000000000000000
+patword 0x0003 0x0000000000000000
+patword 0x0004 0x0000000000000000
+patword 0x0005 0x0000000000000000
+patword 0x0006 0x0000000000000000
+patword 0x0007 0x0000000000000000
+patword 0x0008 0x0000000000000000
+patword 0x0009 0x0000000000000000
+patword 0x000a 0x0000000000000000
+patword 0x000b 0x0000000000000000
+patword 0x000c 0x0000000000000000
+patword 0x000d 0x0000000000001000
+patword 0x000e 0x0000000000001000
+patword 0x000f 0x0000000000001000
+patword 0x0010 0x0000000000001000
+patword 0x0011 0x0000000000001000
+patword 0x0012 0x0000000000000000
+patword 0x0013 0x0000000000000000
+patword 0x0014 0x0000000000000000
+patword 0x0015 0x0000000000000000
+patword 0x0016 0x0000000000000000
+patword 0x0017 0x0000000000000400
+patword 0x0018 0x0000000000000400
+patword 0x0019 0x0000000000000400
+patword 0x001a 0x0000000000000400
+patword 0x001b 0x0000000001000400
+patword 0x001c 0x0000000001000400
+patword 0x001d 0x0000000001000400
+patword 0x001e 0x0000000001000400
+patword 0x001f 0x0000000000000400
+patword 0x0020 0x0000000000000400
+patword 0x0021 0x0000000000000400
+patword 0x0022 0x0000000000000400
+patword 0x0023 0x0000000000001400
+patword 0x0024 0x0000000000001400
+patword 0x0025 0x0000000000001400
+patword 0x0026 0x0000000000001400
+patword 0x0027 0x0000000001001400
+patword 0x0028 0x0000000001001400
+patword 0x0029 0x0000000001001400
+patword 0x002a 0x0000000001001400
+patword 0x002b 0x0000000000001400
+patword 0x002c 0x0000000000001400
+patword 0x002d 0x0000000000001400
+patword 0x002e 0x0000000000001400
+patword 0x002f 0x0000000000000400
+patword 0x0030 0x0000000000000400
+patword 0x0031 0x0000000000000400
+patword 0x0032 0x0000000000000400
+patword 0x0033 0x0000000000000400
+patword 0x0034 0x0000000000000400
+patword 0x0035 0x0000000000000400
+patword 0x0036 0x0000000000000400
+patword 0x0037 0x0000000000000000
+patioctrl 0x0000000001b3ffff
+patlimits 0x0000 0x0037
+patloop 0 0x0018 0x0036
+patnloop 0 192
+patloop 1 0x0400 0x0400
+patnloop 1 0
+patloop 2 0x0400 0x0400
+patnloop 2 0
+patloop 3 0x0400 0x0400
+patnloop 3 0
+patloop 4 0x0400 0x0400
+patnloop 4 0
+patloop 5 0x0400 0x0400
+patnloop 5 0
+patwait 0 0x0400
+patwaittime 0 0
+patwait 1 0x0400
+patwaittime 1 0
+patwait 2 0x0400
+patwaittime 2 0
+patwait 3 0x0400
+patwaittime 3 0
+patwait 4 0x0400
+patwaittime 4 0
+patwait 5 0x0400
+patwaittime 5 0

slsDetectorServers/xilinx_ctbDetectorServer/reset_chip_xilinx.txt

@@ -1,30 +1,30 @@
 
 # turn off clock
-setbit 0xB1B0 16 
-setbit 0xB1B8 0
+setbit 0xC00C 16 
+setbit 0xC014 0
 sleep 1
 
 # reset Matterhorn periphery
-setbit 0xB1B8 1
+setbit 0xC014 1
 sleep 1
 
 # turn on clock
-clearbit 0xB1B0 16
-setbit 0xB1B8 0
+clearbit 0xC00C 16
+setbit 0xC014 0
 sleep 1
 
 # reset rx transceiver datapath
-setbit 0xB820 4
+setbit 0xC120 4
 sleep 1
 
 # reset 8b10b counters
-setbit 0xB820 9
-setbit 0xB820 10
-setbit 0xB820 11
-setbit 0xB820 12
+setbit 0xC120 9
+setbit 0xC120 10
+setbit 0xC120 11
+setbit 0xC120 12
 sleep 1
-clearbit 0xB820 9
-clearbit 0xB820 10
+clearbit 0xC120 9
+clearbit 0xC120 10
 
 # reset buffer fifos
 reg 0x9024 0xFFFFFFFF

slsDetectorSoftware/tests/CMakeLists.txt

@@ -8,7 +8,6 @@ target_sources(tests PRIVATE
 
     ${CMAKE_CURRENT_SOURCE_DIR}/Caller/test-Caller.cpp
     ${CMAKE_CURRENT_SOURCE_DIR}/Caller/test-Caller-rx.cpp
-    ${CMAKE_CURRENT_SOURCE_DIR}/Caller/test-Caller-rx-running.cpp
     ${CMAKE_CURRENT_SOURCE_DIR}/Caller/test-Caller-pattern.cpp
     ${CMAKE_CURRENT_SOURCE_DIR}/Caller/test-Caller-eiger.cpp
     ${CMAKE_CURRENT_SOURCE_DIR}/Caller/test-Caller-jungfrau.cpp

slsDetectorSoftware/tests/Caller/test-Caller-rx-running.cpp

@@ -1,72 +0,0 @@
-// SPDX-License-Identifier: LGPL-3.0-or-other
-// Copyright (C) 2025 Contributors to the SLS Detector Package
-#include "Caller.h"
-#include "catch.hpp"
-#include "sls/Detector.h"
-#include "tests/globals.h"
-
-#include <sstream>
-
-namespace sls {
-
-using test::PUT;
-
-/*
-detfuncs::F_RECEIVER_SET_NUM_FRAMES
-detfuncs::F_RECEIVER_SET_NUM_TRIGGERS
-detfuncs::F_RECEIVER_SET_NUM_BURSTS
-detfuncs::F_RECEIVER_SET_TIMING_MODE
-detfuncs::F_RECEIVER_SET_BURST_MODE
-detfuncs::F_RECEIVER_SET_NUM_ANALOG_SAMPLES
-detfuncs::F_RECEIVER_SET_NUM_DIGITAL_SAMPLES
-detfuncs::F_RECEIVER_SET_NUM_TRANSCEIVER_SAMPLES
-detfuncs::F_RECEIVER_SET_DYNAMIC_RANGE
-detfuncs::F_RECEIVER_SET_STREAMING_FREQUENCY
-detfuncs::F_RECEIVER_SET_FILE_INDEX
-detfuncs::F_RECEIVER_SET_FILE_WRITE
-detfuncs::F_RECEIVER_SET_MASTER_FILE_WRITE
-detfuncs::F_RECEIVER_SET_OVERWRITE
-detfuncs::F_RECEIVER_ENABLE_TENGIGA
-detfuncs::F_RECEIVER_SET_FIFO_DEPTH
-detfuncs::F_RECEIVER_SET_ACTIVATE
-detfuncs::F_RECEIVER_SET_STREAMING
-detfuncs::F_RECEIVER_SET_STREAMING_TIMER
-detfuncs::F_RECEIVER_SET_FLIP_ROWS
-detfuncs::F_RECEIVER_SET_DBIT_LIST
-detfuncs::F_RECEIVER_SET_DBIT_OFFSET
-detfuncs::F_RECEIVER_SET_DBIT_REORDE
-*/
-
-auto get_test_parameters() {
-    return GENERATE(
-        std::make_tuple("asamples", std::vector<std::string>{"5"}),
-        std::make_tuple("tsamples", std::vector<std::string>{"2"}),
-        std::make_tuple("dsamples", std::vector<std::string>{"100"}),
-        std::make_tuple("frames", std::vector<std::string>{"10"}),
-        std::make_tuple("triggers", std::vector<std::string>{"5"}),
-        std::make_tuple("rx_dbitlist", std::vector<std::string>{"{1,2,10}"}),
-        std::make_tuple("rx_dbitreorder", std::vector<std::string>{"0"}),
-        std::make_tuple("rx_dbitoffset", std::vector<std::string>{"5"}),
-        std::make_tuple("findex", std::vector<std::string>{"2"}),
-        std::make_tuple("fwrite", std::vector<std::string>{"0"}),
-        std::make_tuple("bursts", std::vector<std::string>{"20"}));
-}
-
-TEST_CASE("cant put if receiver is not idle", "[.cmdcall][.rx]") {
-    auto [command, function_arguments] = get_test_parameters();
-
-    Detector det;
-    Caller caller(&det);
-
-    // start receiver
-    std::ostringstream oss;
-    caller.call("rx_start", {}, -1, PUT, oss);
-    REQUIRE(oss.str() == "rx_start successful\n");
-
-    REQUIRE_THROWS(caller.call(command, function_arguments, -1, PUT, oss, -1));
-
-    std::ostringstream oss_stop;
-    caller.call("rx_stop", {}, -1, PUT, oss_stop);
-    REQUIRE(oss_stop.str() == "rx_stop successful\n");
-}
-} // namespace sls

slsReceiverSoftware/src/ClientInterface.cpp

@@ -551,7 +551,6 @@ int ClientInterface::set_num_analog_samples(Interface &socket) {
     if (detType != CHIPTESTBOARD && detType != XILINX_CHIPTESTBOARD) {
         functionNotImplemented();
     }
-    verifyIdle(socket);
     try {
         impl()->setNumberofAnalogSamples(value);
     } catch (const std::exception &e) {
@@ -568,7 +567,6 @@ int ClientInterface::set_num_digital_samples(Interface &socket) {
     if (detType != CHIPTESTBOARD && detType != XILINX_CHIPTESTBOARD) {
         functionNotImplemented();
     }
-    verifyIdle(socket);
     try {
         impl()->setNumberofDigitalSamples(value);
     } catch (const std::exception &e) {
@@ -1738,7 +1736,6 @@ int ClientInterface::set_num_transceiver_samples(Interface &socket) {
     if (detType != CHIPTESTBOARD && detType != XILINX_CHIPTESTBOARD) {
         functionNotImplemented();
     }
-    verifyIdle(socket);
     try {
         impl()->setNumberofTransceiverSamples(value);
     } catch (const std::exception &e) {

tests/scripts/test_simulators.py

@@ -22,7 +22,7 @@ class RuntimeException (Exception):
         super().__init__(Log(Fore.RED, message))
     
 def checkIfProcessRunning(processName):
-    cmd = f"pgrep {processName}"
+    cmd = f"pgrep -f {processName}"
     res = subprocess.getoutput(cmd)
     return res.strip().splitlines()
 
@@ -199,9 +199,9 @@ with open(fname, 'w') as fp:
     Log(Fore.BLUE, 'General tests (results: ' + file_results + ')')
 
     try:
-        cleanup(fp)
         startGeneralTests(fp, file_results)
-        
+        cleanup(fp)
+
         testError = False
         for server in servers:
             try: