* add patternstart command for CTB, block end of execution udp packets if pattern was started by patternstart command
* update docs
* Dhanya's comments
* more Dhanya comments
* refactored
* fixed tests for startpatttern, also clkfrequency not properly used in server
* xilinx: fixed setfrequency, tick clock (with sync clock), clkfrequency set from getfrequency to get the exact value
* xilinx freq in kHz, updated default values and prints
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Co-authored-by: Martin Mueller <martin.mueller@psi.ch>
Co-authored-by: Dhanya Thattil <dhanya.thattil@psi.ch>
* update ctb regDefs, included fill level of adc, transceiver and DBit fifos, added enable registers for cont. readout
* fix fifo fill level range bug
* updated ctb RegDefs, increased size of fifo fill level register
* added register to read the firmware git hash
* ctb: added altchip_id read register
* start with unification of pattern machinery for xctb, ctb, mythen
* udate addrs for d-server internal matterhorn startup
* update xctb reg defs
* move pattern loopdef start
* added zero trimbits to matterhorn config
* Revert "added zero trimbits to matterhorn config"
This reverts commit 7c347badd5.
* added adjustable clocks on Xilinx-CTB
* added support for fractional dividers of runclk
* XCTB: make frequencies adjustable from python gui
* update docs
* added support for patternstart command to XCTB
* XCTB: map pattern_ram directly into memory, removed rw strobe
* refactor Mythen pattern control addresses
* test altera ctb with common addresses, removed ifdefs
* change ordering of regdefs
* updated python help for dbitclk, adcclk and runclk (khz)
* xilinx: moved the wait for firmware to measure the actual frequency to the server side and removed it in the pyctbgui side
* will not be anymore in developer branch
* make format (exception RegisterDefs.h), rewrite XILINX PLL to have less consstants in the code
* bug: mixing && for &
---------
Co-authored-by: Martin Mueller <martin.mueller@psi.ch>
Co-authored-by: Dhanya Thattil <dhanya.thattil@psi.ch>
* updated RegisterDefs.h from firmware update
* Revert "updated RegisterDefs.h from firmware update"
This reverts commit 64f1b2546e.
* updated registers and had it formatted
* Revert "updated registers and had it formatted"
This reverts commit 1641b705b0.
* udpated registers from firmware, reading config file in server (chip config, reset chip, enable_clock_pattern) specific for matterhorn,this is done when powering on chip, removed startreadout, fixed status register bits, updated firmware version
* fix for patioctrl allowed for zxilinx and adding readout pattern for scientists that like to push the acquire button
* fixing default enable clock and readout pattern for xilinx (patioctrl has to be 32 bit)
* Xilinxctb/first image (#1094)
* reduce xilinxCTB readout done checks to single register, increased clockEna pattern limits, clear FPGA FiFos and counters on powerchip, disable counters 1-3 in matterhorn configuration
* change print of xilinxctb server
* remove acquisition done check
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Co-authored-by: Martin Mueller <martin.mueller@psi.ch>
* binary xilinx in
* formatting
* added reset of udp buffer FIFO to xilinxCTB
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Co-authored-by: Martin Mueller <72937414+mmarti04@users.noreply.github.com>
Co-authored-by: Martin Mueller <martin.mueller@psi.ch>
* cli: patwaittime also takes time argument, api: patwaitclocks and patwaitinterval, tcp: patwaitinterval is 2 functions for set and get, patwaitclocks remains a single for backward compatibility with -1 for get, server (loadpattern): clks using member names (needs to be refactored). needs tobe discussed what to do with pattern files.
* all tests passed
* fixed test
* exptime deprecated for ctb and xilinx
* pyctbgui..not there yet
* fixed in pyctbgui
* removed redundant warning for ctb and xilinx exptime in Detector class (already in module class handling all exptime signatures), patwait, patloop and patnloop have to be non inferrable commands because of support for old commands (level as suffix)
* fix formatting error from command line parsing
* fix tests for patwaittime
* period and exptime(patternwaittime level 0)
* added new regsieterdefs and updated api version and fixedpattern reg
* autogenerate commands
* formatting
* minor
* wip resetflow, readout mode, transceiver mask, transceiver enable
* acquisition, but streaming done bit and busy (exposing + read chip to fifo) not known yet from fw
* programming fpga and device tree done
* most configuration done, need to connect configuretransceiver to client
* stuck at resetting transciever timed out
* minor
* fixed virtual, added chip busyto fifo, streaming busy, set/getnext framenumber
* configuretransceiver from client, added help in client
* make formatt and command generation
* tests for xilinx ctb works
* command generation
* dacs added and tested, power not done
* power added
* added temp_fpga
* binaries in
* ctrlreg is 0 to enable chip=fixed, high dac val = min val= fixed, power regulators in weird order=fixed, device tree could be loaded with dacs before adcs=fixed
* start works
* virtual server sends
* receiver works
* tests
* python function and enum generation, commands generatorn and autocomplete, formatting, tests
* tests fail at start(transceiver not aligned)
* tests passed
* all binaries compiled
* eiger binary in
* added --nomodule cehck for xilinx
* implemented testbus, testfpga, set/get #frames, triggers, allowed that and for connection to client, also allowed, getnumchannels, configuremac, getrunstatus, setdetectorposition with dummy values
* connected kernelversion, hardwareversion, versions, framesl, triggersl, dr, timingmode, pattern (except patioctrl) thats there for altera ctb
* replaced set/get64Bit to set/getU64bit in all loadpattern.c for (ctb and m3 also)
* when dbit list is enabled, the size of data in zmq stream is changed to only the digital bits enabled size. now fixed to also include analog size
* allowing to set 0xffffffffffffffff to pat io control. prevously was used to do a get. fixed also for pat bit mask and pat mask
* copied jungfrau server to moench and adapted
* fixed image size and num packets
* read n rows allows 16
* commneted out configure_asic_timer at server startup. To be removed later the ASIC_CTRL_REG and storage cell options
* moench:removing the decrement (which was in jf) in read n rows to register
* removed lblsamples from gui
* badchannels for m3 and modify for g2 (file from single and multi)
* m3: invert polarity of bit 7 and 11 signals from setmodule, allow commas in bad channel file
* badchannel file can take commas, colons and comments (also taking care of spaces at the end of channel numbers)
* tests 'badchannels' and 'Channel file reading' added, removing duplicates in badchannel list, defining macro for num counters in client side
* fix segfault when list from file is empty,
* fix tests assertion for ctbconfig (adding message) for c++11
* fixed badchannels in m3server (clocking in trimming)
* badchannel tests can be run from any folder (finds the file)
* separating pattern levels from command name: command line done
* separated patten level from command in examples and default pattern files in servers
* command line and server works
* python: patnloop not verified, wip
* works except for patloop (set, and get does not list properly)
* minor
* fixed tests
* added 3 more levels for ctb and moench
* wip
* minor err msg
* minor
* binaries in
* separating pattern levels from command name: command line done
* separated patten level from command in examples and default pattern files in servers
* command line and server works
* python: patnloop not verified, wip
* works except for patloop (set, and get does not list properly)
* minor
* fixed tests
* added 3 more levels for ctb and moench
* wip
* minor err msg
* minor
* binaries in
* python working
* import fix
* changed fw version for ctb and moench. binaries in
Co-authored-by: Erik Frojdh <erik.frojdh@gmail.com>
