* update ctb regDefs, included fill level of adc, transceiver and DBit fifos, added enable registers for cont. readout
* fix fifo fill level range bug
* updated ctb RegDefs, increased size of fifo fill level register
* added register to read the firmware git hash
* ctb: added altchip_id read register
* start with unification of pattern machinery for xctb, ctb, mythen
* udate addrs for d-server internal matterhorn startup
* update xctb reg defs
* move pattern loopdef start
* added zero trimbits to matterhorn config
* Revert "added zero trimbits to matterhorn config"
This reverts commit 7c347badd5.
* added adjustable clocks on Xilinx-CTB
* added support for fractional dividers of runclk
* XCTB: make frequencies adjustable from python gui
* update docs
* added support for patternstart command to XCTB
* XCTB: map pattern_ram directly into memory, removed rw strobe
* refactor Mythen pattern control addresses
* test altera ctb with common addresses, removed ifdefs
* change ordering of regdefs
* updated python help for dbitclk, adcclk and runclk (khz)
* xilinx: moved the wait for firmware to measure the actual frequency to the server side and removed it in the pyctbgui side
* will not be anymore in developer branch
* make format (exception RegisterDefs.h), rewrite XILINX PLL to have less consstants in the code
* bug: mixing && for &
---------
Co-authored-by: Martin Mueller <martin.mueller@psi.ch>
Co-authored-by: Dhanya Thattil <dhanya.thattil@psi.ch>
* transceiverenable, tsamples, romode for tranceiver and digital_transceiver
* 202 spec instr only for transceiver mode
* removed check for empty in trans readout and clean memory before reading from fifo
* ctb read fifo strobe for all after reading all channels, adding 1us after selecting channel, changing fw date
* updated 10gb transceiver enable
----
* added transceiver (tsamples, romode(transceiver, digital_transceiver), transceiverenable (mask)
* clean memory before reading from fifo (for analog and digital as well)
* read fifo then read strobe (also corresp fw) fixes number of reads (also for analg and digital)-> increases all pipelines by 1
* fixed bug in rearranging digital data in receiver
* fixed bug in streaming size of data after rearranging
* fixed bug in setbit, clearbit,and getbit
* status checks fifo before returning idle (transmitting if data in fifo if transceiver more enabled)
* soem matterhorn specifics that will need to be put into pattern in a month or two. this is temporary.
* NOTE: breaking api. rxParameters struct has transceiverenabel and tsamples given from det to receiver
Firmware updated. spi moved to firmware. In Software, configuring, then a pulse to start, wait for done bit and convert the values read from a regiter.
* separating pattern levels from command name: command line done
* separated patten level from command in examples and default pattern files in servers
* command line and server works
* python: patnloop not verified, wip
* works except for patloop (set, and get does not list properly)
* minor
* fixed tests
* added 3 more levels for ctb and moench
* wip
* minor err msg
* minor
* binaries in
* separating pattern levels from command name: command line done
* separated patten level from command in examples and default pattern files in servers
* command line and server works
* python: patnloop not verified, wip
* works except for patloop (set, and get does not list properly)
* minor
* fixed tests
* added 3 more levels for ctb and moench
* wip
* minor err msg
* minor
* binaries in
* python working
* import fix
* changed fw version for ctb and moench. binaries in
Co-authored-by: Erik Frojdh <erik.frojdh@gmail.com>
