330 Commits

Author SHA1 Message Date
e5ee27dbfa
8.0.0.rc jf: reconfigure chip when touching electron collection mode bit (#830)
* jf: if bit 14 in reg 0x5d (electron mode collection bit) is changed, configure chip if v1.1 and powered on. so touch writeregister (setbit/clearbit also calls write register in the end). replace when electroncollectionmode command introduced
2023-10-18 10:49:44 +02:00
601249cc71
8.0.0.rc jf: change status reg bits (#828)
* rewrite of status reg bits, waiting state includes both wati for trigger and start frame, blocking trigger only waits if its not in waiting for trigger and run busy enabled, error state connected in firmware
2023-10-18 10:36:56 +02:00
d003a6d8e0
2. Dev/add jf pedestal feature (#807) 2023-09-29 11:25:58 +02:00
9834b07b47
Dev/fix port size (#805)
* port datatype changing from int to uint16_t
* throwing for -1 given for uint16_t ports
2023-09-28 09:36:39 +02:00
77d13f0794 updated all servers as my3 was not updated and had api issues 2023-08-29 11:11:19 +02:00
1873cc9310
Moench dacs defaults (#788)
* merge fix from 7.0.2: new jungfrau fw versions, incremented binary, hdf5 and json versions

* moench: changed dac names and default values to old moench values

* moench: remove interface clk polarity at start up

* moench: default speed is half speed, default values for adc offset and adc phase for different speeds (only half speed confirmed), adc vref voltage to 2.0 like G1

* moench: connected adc pipeline to client

* moench: receiver- default frames per file is 100k and discard partial frames as default

* moench binary in

* using tostring in gui for dacs

* moved frame discard policy as a parameter to be configured with a default depending on detector

* moench: 300 degrees for adc phase in full speed
2023-07-31 14:02:30 +02:00
d5ce03918c
ctb: allowing adc enable for 10g to be 0, romode changing bit from disable analog to enable analog, removing matterhorn specific (#789) 2023-07-25 10:33:18 +02:00
36a9bafbde
merge fix from 7.0.2: new jungfrau fw versions, incremented binary, hdf5 and json versions (#786) 2023-07-20 09:30:42 +02:00
71489b7106
2. Set row col (#779)
* set row and column
2023-07-18 15:51:22 +02:00
c628ae2192
1. Ctb transceiver ro (#773)
*  transceiverenable, tsamples, romode for tranceiver and digital_transceiver

* 202 spec instr only for transceiver mode

* removed check for empty in trans readout and clean memory before reading from fifo

* ctb read fifo strobe for all after reading all channels, adding 1us after selecting channel, changing fw date

* updated 10gb transceiver enable

----
* added transceiver (tsamples, romode(transceiver, digital_transceiver), transceiverenable (mask)

* clean memory before reading from fifo (for analog and digital as well)

* read fifo then read strobe (also corresp fw) fixes number of reads (also for analg and digital)-> increases all pipelines by 1

* fixed bug in rearranging digital data in receiver

* fixed bug in streaming size of data after rearranging

* fixed bug in setbit, clearbit,and getbit

* status checks fifo before returning idle (transmitting if data in fifo if transceiver more enabled)

* soem matterhorn specifics that will need to be put into pattern in a month or two. this is temporary.

* NOTE: breaking api. rxParameters struct has transceiverenabel and tsamples given from det to receiver
2023-07-14 16:29:21 +02:00
5be503c1bd
moench speeds (#776)
* added other speeds and updated readoutspeedlist, test, gui
2023-07-10 15:09:51 +02:00
58cdb5bd20
added patfname command to save the file the last pttern was loaded from (#770)
* added patfname command to save the file the last pttern was loaded from
2023-06-22 09:08:48 +02:00
d3d98db7e9
1. Ctb powerindices (#767)
* power and sense returning dac indices instead of int in Detector class
2023-06-19 15:19:50 +02:00
3f9ec695db
2. Patioctrl uint64 t (#766)
* when dbit list is enabled, the size of data in zmq stream is changed to only the digital bits enabled size. now fixed to also include analog size

* allowing to set 0xffffffffffffffff to pat io control. prevously was used to do a get. fixed also for pat bit mask and pat mask
2023-06-15 09:30:52 +02:00
a5f26252b8
ctb v_limit dac tristate (#761)
* ctb: allowing dac to tristate (-100) even if v_limit is set

* binary in

* formatting
2023-06-15 08:42:42 +02:00
95d89522d8 formatting 2023-05-25 12:10:46 +02:00
6fcb880538
Merge fix from 7.0.2 (#756)
- start acq list: mixup with master pos #743 : fix that only master starts second and not all (for start acq), typo with pos and masters list
- synced master status running when setting to slave  #747: synced master status running when setting to slave
2023-05-25 11:20:41 +02:00
65b8c9c5c1
Moench rw3 (#745)
* moench, removed chip version, filter resistor, filter cells, currentsoures, gain mode, setttings(modes), dbitphase, maxdbitphase, autocompdisable, comparatordisabletime, made acq start and stop a pulse, removed unused registers

* added parallel command

* remove gain plot for moench

* moench: updated adc invert val

* moench: update adcoffset to 0xf and adcphase to 140 degrees

* removed sync clock in moench

* updated min fw version

* removing config file in moench server
2023-05-25 11:00:23 +02:00
0a7fd0a51a
set bit and clear bit only verifies that bit (#746) 2023-05-25 10:35:17 +02:00
afee45790f
1. allow 1gbe non blocking acquire by creating another thread (#753)
* allow 1gbe non blocking acquire by creating another thread

* removed unnnecessary print out in ctb
2023-05-24 13:39:40 +02:00
a0f250a487
Ctb: allow adc mask enable to be 0 for 1 and 10GbE (#750)
* ctb: allow adc mask enable to be 0 for 1 and 10GbE
2023-05-22 11:26:57 +02:00
da4dd0df7e
Formatting (#742) 2023-05-11 10:17:24 +02:00
e757e25fa1
merge fix #721 PR (sync 7.0.2.rc) to developer (#739)
* merge fix from #721 PR (sync) 7.0.2.rc -> developer
* row and column for jungfrau mixed up

* multi module jungfrau sync must do slaves first then master for start acquisition and send software trigger, and master first and then slaves for stopacquisition

* non blocking to slaves first and only then blocking/nonblocking to the master for sending software trigger(jungfrau multi mod sync)

* fixed get/set timing jungfrau when sync enabled, getsync during blocking acquire (for trigger or stop) will get stuck as it should ask the stop server

* switching between 1 and 2 interfaces did not set gui/client zmq port properly. Resulted in dummy streaming forever. fixed

* formatting, refactoring: const & for positions, multi mod M3 stop first master first

* adding missing cstdint for gcc 13

* Refactoring handle sync out, handling synchronization also for softwaretrigger for m3, for start/sync/stop for g2/g1

---------

Co-authored-by: Erik Frojdh <erik.frojdh@gmail.com>

* fixed row and col for moench 2 interfaces

* fix moench getTiming and also allow moench to handle sync

---------

Co-authored-by: Erik Frojdh <erik.frojdh@gmail.com>
2023-05-08 15:58:19 +02:00
fc24558314 formatting 2023-03-17 14:42:11 +01:00
Dhanya Thattil
d23722a4b7
Eiger: add hardware version (#688)
* eiger: hardwareversion, fix firmware version unable to read version scenarios, check to see if febl, febr and beb have same fw version

* feb versions can be picked up only after feb initialization
2023-03-16 11:59:06 +01:00
21db57dd89 binaries in 2023-02-24 10:44:17 +01:00
dc5db905d4 merge from 7.0.0 2023-02-24 10:39:51 +01:00
Dhanya Thattil
48a684b95f
dev:Eiger febl febr (#601)
* eiger: get febl and febr versions in versions command, also added in python
2023-02-24 10:06:11 +01:00
Dhanya Thattil
276dc52196
dev:removed storage cells for moench (#603)
* removed storage cells for moench
* rxr: also setting moench like jungfrau in implementation of ports
2023-02-24 10:00:31 +01:00
90496bcee8 updated release date and lib api date 2023-02-23 16:38:10 +01:00
13bbd54a21 formatting 2023-02-22 11:42:06 +01:00
d84e9652d3 updated versions for the servers 2023-02-22 11:36:47 +01:00
1ce39c48c7 updated client versions 2023-02-22 11:29:58 +01:00
Dhanya Thattil
8501e1fb1f
eiger server moved to fw 31 (#681)
* eiger server moved to fw 31
2023-02-22 11:10:56 +01:00
Dhanya Thattil
adcde9fd49
user friendly message added from ' dangerous to continue' to 'check firmware' (#665) 2023-02-20 16:35:33 +01:00
Dhanya Thattil
b200a2efc1
Fix jf softwre trigger and tests with real jungfrau detector (#673)
* jungfrau: software triggers do not work, fixed

* eiger test: get highvoltage must be read twice to get the real voltage
2023-02-20 15:22:46 +01:00
cb8e4365e3 formatting 2023-02-14 15:08:31 +01:00
7c047cab4a udpated version to rc4 2023-02-14 10:30:45 +01:00
d90bf6c7df formatting 2023-02-13 11:36:41 +01:00
e6505650cb proper update of client and rx versions to 7.0.0.rc3 2023-02-10 16:34:04 +01:00
ba6fdb9695 udpated client and rx versions to rc3 2023-02-10 16:04:32 +01:00
Dhanya Thattil
55bf73f3b7
unicast udp_srcmac (#642)
* udp_srcmac can only be a unicast address (LSB of first octet must be 0)

* renamed binaries
2023-02-03 10:56:19 +01:00
Dhanya Thattil
c62ce0ce6b
m3:changed str_clk (clkdiv 3) default to 166MHz (6) (#643) 2023-01-30 17:05:42 +01:00
Dhanya Thattil
3a3628c475
m3 firmware version change (#637)
* m3 firmware version change

* changed binary name to rc3
2023-01-27 10:54:45 +01:00
Dhanya Thattil
3f7c9529dd
m3: changed clk 0 1 2 to 100MHz (#636)
* m3: changed clk 0 1 2 to 100MHz

* m3:fix clk 2

* binaries in
2023-01-25 11:54:37 +01:00
0b17318f10 formatting 2023-01-24 10:37:52 +01:00
3bf6be41b4 merge from 7.0.0.rc 2023-01-17 09:48:59 +01:00
Dhanya Thattil
7466c0bc8f
M3 deserialize (#618)
* m3: updated serializing loop in trimming

* fixed the deserializing loop again
2023-01-17 09:39:58 +01:00
Dhanya Thattil
713639d001
Fix gotthard delay (#606)
* fix for set delay for gotthard1 (verification adds master delay even if its not master)

* binaries in

* binaries name
2023-01-17 09:16:43 +01:00
Dhanya Thattil
22b3229d94
m3: updated serializing loop in trimming (#613) 2023-01-16 13:43:28 +01:00