c64b09ee79
Jungfraufix ( #84 )
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* jungfrau: added dbitphase, different pll clkindex 0 with different wr bit
2020-03-04 17:06:18 +01:00
maliakal_d
8abc32e7f1
moench: default pattern file in server, settings, tests
2020-03-03 16:00:01 +01:00
maliakal_d
6bbcf6173d
moench: first version
2020-03-02 18:34:10 +01:00
11e7737a2f
gotthard2: timingsource and currentsource features, (timing source external yet to be implemented in fpga to test ( #80 )
2020-02-28 12:45:02 +01:00
maliakal_d
6a0a931e3e
gotthard2: bursts and burst period, written to same register as triggers and delay (kept in server as variables) and set if conditions meet. bursts and burst period only in auto timing and burst mode. Also updating theses registers when switching between timing modes or burst modes
2020-02-25 15:45:40 +01:00
maliakal_d
d3dc9a7690
gotthard2: disentangled burst mode #frames, exptime, period from start of acquisition, order dependent now for debugging
2020-02-04 12:23:58 +01:00
maliakal_d
89c774dbf7
nios programming: check file size first
2020-01-31 11:24:48 +01:00
5ca3a1b685
gotthard2 and mythen3: programming fpga, reboot; jungfrau, ctb: modified programming ( #74 )
2020-01-30 19:52:35 -08:00
maliakal_d
a9e375ed34
gotthard2: bursttype to burstmode
2020-01-23 11:03:14 +01:00
maliakal_d
8cbf3c62a9
merge from developer
2020-01-22 17:30:13 +01:00
maliakal_d
981b13494c
mythen3: virtual server, connected timing mode, row and col in header, included pattern bit and mask
2020-01-21 18:16:27 +01:00
maliakal_d
e746256653
gotthard2: gain updated
2020-01-21 16:01:38 +01:00
maliakal_d
6cfd0f8962
gotthard2: first edit
2020-01-20 12:13:23 +01:00
maliakal_d
e8bdf5a505
gotthard2: updated register map; powerchip checking detector type; internal and external period, frames, exptime; set/get delay, get actualtime, measurement, framesfromstart enabled; which detector comment updated in cmdproxy, detector and slsdetector
2020-01-16 15:33:35 +01:00
de53747ddd
Counters ( #71 )
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* mythen3: adding counters mask, firmware still takes only number of counters for now
* mythen3: checking if module attached before powering on chip
* bug fix: loop inital declaration not allowed in c
* fix scope eiger test
* mythen3: renamed setCounters to setCounterMask and getCounterMask in API
* mythen3 replacing counting bits with popcount
Co-authored-by: Erik Fröjdh <erik.frojdh@gmail.com >
2020-01-14 17:40:46 +01:00
maliakal_d
3486137de3
bfin warnings fixed
2019-11-27 18:22:33 +01:00
maliakal_d
9455a5fba1
ctb: adcenable10g included, 10g readout enables included
2019-11-27 17:28:57 +01:00
maliakal_d
d07873ee39
mythen3 and gotthard2: wait request not needed, reset to be implemented
2019-11-22 11:29:24 +01:00
maliakal_d
dfc886a65b
mythen3 gui
2019-11-18 17:57:19 +01:00
maliakal_d
6a27207875
gotthard2: vetoref, burstmode
2019-11-15 18:59:27 +01:00
maliakal_d
5518531620
gotthard2: veto reference
2019-11-14 19:01:10 +01:00
maliakal_d
28a5aa8342
injectchannel WIP
2019-11-13 15:11:11 +01:00
maliakal_d
90c34e4942
gotthard2, dacs and onchip dacs from config file
2019-11-11 18:02:08 +01:00
maliakal_d
bb26b993ea
servers, firmware check message to init message, minor
2019-11-11 12:00:04 +01:00
maliakal_d
03ec2c53ab
WIP
2019-11-08 17:10:28 +01:00
maliakal_d
d7e2ab8ec4
gotthard2: on chip dacs
2019-11-08 17:09:57 +01:00
maliakal_d
1797d39216
updated mythen3 to configure phase, freq, delay left, period left, actual time, measurement time, framesfrom start and othe register mappings
2019-11-06 18:58:22 +01:00
maliakal_d
73b5c3ac57
merge
2019-11-06 16:46:00 +01:00
maliakal_d
18b8720c17
separated parameters and versions
2019-11-06 16:43:59 +01:00
7de9401bc7
powerchip for mythen3
2019-11-06 11:50:09 +01:00
maliakal_d
1f64d2a4e2
speed separated
2019-11-05 18:50:35 +01:00
maliakal_d
031241ae28
timer split up
2019-11-04 16:40:11 +01:00
maliakal_d
6c5c4f00b3
mythen3 calc checksum
2019-10-31 12:31:51 +01:00
maliakal_d
11ea071543
adcinvert for jungfrau, gui for jungfrau dacs
2019-10-30 12:28:51 +01:00
maliakal_d
f4a0780b51
patloops done
2019-10-24 18:59:23 +02:00
995f0924e5
Commandline ( #66 )
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* WIP
* WIP
* removed status to string from defs
* WIP
* WIP
* WIP removed unused functions in multi
* WIP
* print hex in a terrible way
* WIP, loadconfig error
* WIP, type to string
* WIP
* fix to conversion
* WIP, hostname doesnt work
* WIP
* WIP
* WIP
* WIP, threshold
* WIP, threshold
* WIP
* WIP, triggers
* WIP, cycles to triggers
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* rx_udsocksize fx, WIP
* WIP
* WIP
* WIP
* file index (64 bit), WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* merge
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* New python mod
2019-10-21 10:29:06 +02:00
maliakal_d
be50344b45
set clock divider, phase and get clock freq for gotthard2, priliminary
2019-10-17 16:39:41 +02:00
maliakal_d
cfd3680176
gotthard2 dacs
2019-10-08 17:10:36 +02:00
maliakal_d
030cfacc9b
WIP
2019-10-08 10:57:07 +02:00
5f94b5c246
Dac ( #67 )
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* dac WIP
* dacs WIP
* DACs are working with names
* namechanges of vrfsh->vshaper, vrfshnpol->vshaperneg
* pattern for MY3, configure MAC for MY3
2019-10-07 12:13:25 +02:00
maliakal_d
0f99dd141e
gotthard 2 server test bus
2019-10-01 17:34:52 +02:00
ca054626e6
Removeudpcache ( #65 )
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* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* solved eiger 1-10g issue
* some fixes for remove udp cache to work
* bug fix virtual
* removed special handling of rx_udpip
2019-09-30 14:46:25 +02:00
6e6fcec698
MY3.0:read and write Registers, frames, cycles, delay ( #64 )
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* MY3.0:read and write Registers, frames, cycles, delay
* write pattern seems to work
* done all corrections. added default clks: run_clk=125MHz, tick_clk=20MHz (fix), sampling_clk=80MHz (from Carlos)
* clk check for aquistition time
* clk check for aquistition time
* Update slsDetectorServer_defs.h
* Update slsDetectorFunctionList.c
2019-09-30 14:36:33 +02:00
maliakal_d
288b59d292
gotthard2 changes for first firmware version
2019-09-26 14:10:11 +02:00
4b987abf41
Niosmarie ( #63 )
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* HV for Mythen3 server
* HV for mythen3 server
* corrected upstreams
* missing endif
2019-09-03 09:36:02 +02:00
5bcde789ac
Readoutflags ( #61 )
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* WIP
* eiger binary back wih versioning
* fixed readout flag in ctbgui, added speedLevel enum
* ctbgui: fixed a print out error
* ctb readout bug fix
* WIP
* WIP
* WIP
2019-09-02 19:27:27 +02:00
maliakal_d
bd95126da2
gotthard2:hv
2019-09-02 12:57:24 +02:00
maliakal_d
9bc6c44e51
hv for strip
2019-08-30 17:53:04 +02:00
maliakal_d
8c15b52b87
nios
2019-08-30 17:28:18 +02:00
0d35b966ff
Separate headers ( #57 )
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* WIP, ctb
* WIP, eiger
* WIP, gotthard
* WIP, jungfrau
* WIP, gotthard2
* WIP, mythen3
* WIP, moench
* fixed gotthard apiversioning mismatch with gotthard2
2019-08-30 11:17:37 +02:00
Dhanya Thattil
maliakal_d