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086cbacd84
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mythen3: connected busy signal insttead of timer
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2019-12-10 11:03:27 +01:00 |
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af9b25fd67
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eiger: validate trimval range
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2019-12-10 10:32:28 +01:00 |
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504fc2d095
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ctb: validate asampes and dsamples > 0 for romode; client: exception caught in acquire to stop receiver and clear busy flag
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2019-12-10 10:25:14 +01:00 |
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5cf1502287
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ctb bug fix: 10g adc enable mask
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2019-12-09 11:30:54 +01:00 |
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2ece6b945e
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rxr: warnings shouldnt throw exception
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2019-11-29 11:09:41 +01:00 |
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3486137de3
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bfin warnings fixed
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2019-11-27 18:22:33 +01:00 |
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9455a5fba1
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ctb: adcenable10g included, 10g readout enables included
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2019-11-27 17:28:57 +01:00 |
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f299a34e59
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ctb server binary update
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2019-11-27 11:31:30 +01:00 |
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6b391a34dc
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gotthard2: bug fix adconfiguration initialization
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2019-11-25 14:14:05 +01:00 |
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94382c1ece
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m3 and g2: while setting clock freq, change phase only if there is a change in phase (removing more printouts, will still only set if needed )
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2019-11-25 10:54:30 +01:00 |
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a95ab1e13e
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servers: default compile not update versionign
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2019-11-22 17:23:07 +01:00 |
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c4675da0c3
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m3: reset fixed
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2019-11-22 16:40:43 +01:00 |
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ba008db29a
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m3 ang g2: reset not yet imple
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2019-11-22 11:54:45 +01:00 |
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950096daf9
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m3 ang g2: reset not yet imple
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2019-11-22 11:54:30 +01:00 |
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d07873ee39
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mythen3 and gotthard2: wait request not needed, reset to be implemented
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2019-11-22 11:29:24 +01:00 |
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f8df11886a
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ctb: change in phase done in degrees (phase reset due to change in frequency)
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2019-11-21 15:08:38 +01:00 |
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d976c9fcf9
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gotthard2: phase direction like mythen3
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2019-11-21 14:41:54 +01:00 |
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c4ae32b216
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mythen3: setting clk frequecy and phase shifts work
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2019-11-21 14:36:37 +01:00 |
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fea94b15d5
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mythen3:forgot binary
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2019-11-21 13:48:39 +01:00 |
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955bc74a91
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mythen3: change vco freq to 1.25GHz
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2019-11-21 13:38:54 +01:00 |
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781e8fc67f
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mythen3: workaround for busy signal
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2019-11-20 11:57:14 +01:00 |
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1cea6af590
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mythen3, gotthard2: change phase, change freq bugfix
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2019-11-19 17:57:28 +01:00 |
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dfc886a65b
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mythen3 gui
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2019-11-18 17:57:19 +01:00 |
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6a27207875
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gotthard2: vetoref, burstmode
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2019-11-15 18:59:27 +01:00 |
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a62d6a2fb8
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gotthard2: veto reference, better code for byte aligment in server
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2019-11-15 11:58:23 +01:00 |
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5518531620
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gotthard2: veto reference
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2019-11-14 19:01:10 +01:00 |
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21d23be522
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gotthard2: inejct channel done
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2019-11-13 16:49:35 +01:00 |
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28a5aa8342
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injectchannel WIP
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2019-11-13 15:11:11 +01:00 |
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72ac2745ea
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gotthard2: server fix enum for onchip dac
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2019-11-12 12:11:52 +01:00 |
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206041989f
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mythen3, reading dr back fix
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2019-11-11 18:33:59 +01:00 |
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2fff9f5bfe
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merge
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2019-11-11 18:03:13 +01:00 |
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90c34e4942
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gotthard2, dacs and onchip dacs from config file
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2019-11-11 18:02:08 +01:00 |
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bb26b993ea
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servers, firmware check message to init message, minor
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2019-11-11 12:00:04 +01:00 |
|
Marie Andrae
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f53d260202
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mythen3: change vph and vpl
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2019-11-11 11:40:06 +01:00 |
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2123fb47a5
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mythen3: config reg enable all counters, dr
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2019-11-11 10:41:42 +01:00 |
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38ad5d7931
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mythen3 rxr
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2019-11-08 18:11:27 +01:00 |
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aaeaeab576
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gotthard2 on chip dacs: -1 should set for all chips
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2019-11-08 17:20:47 +01:00 |
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03ec2c53ab
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WIP
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2019-11-08 17:10:28 +01:00 |
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d7e2ab8ec4
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gotthard2: on chip dacs
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2019-11-08 17:09:57 +01:00 |
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a92d931a8f
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mythen3 frequency fixes
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2019-11-07 14:35:13 +01:00 |
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615b3b2557
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WIP
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2019-11-06 19:07:00 +01:00 |
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1797d39216
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updated mythen3 to configure phase, freq, delay left, period left, actual time, measurement time, framesfrom start and othe register mappings
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2019-11-06 18:58:22 +01:00 |
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0f9fd5cd73
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rename of clkdivider to clkfrequency in servers
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2019-11-06 16:58:34 +01:00 |
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73b5c3ac57
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merge
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2019-11-06 16:46:00 +01:00 |
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18b8720c17
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separated parameters and versions
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2019-11-06 16:43:59 +01:00 |
|
Marie Andrae
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7de9401bc7
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powerchip for mythen3
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2019-11-06 11:50:09 +01:00 |
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705ddb7f42
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WIP
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2019-11-06 11:11:57 +01:00 |
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cd5d327988
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virtual servers updated
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2019-11-06 11:09:48 +01:00 |
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c3180737ed
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fixed jungfau virtual server as well
|
2019-11-06 11:05:02 +01:00 |
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ba37a51858
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eiger virtual server exptime fixed
|
2019-11-06 10:54:33 +01:00 |
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