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7f7a691b25
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fix test
|
2021-11-25 10:19:48 +01:00 |
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|
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00d63e48bb
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fix tests
|
2021-11-25 10:14:49 +01:00 |
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|
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44424bcbe3
|
fix
|
2021-11-25 09:36:50 +01:00 |
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|
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3570795469
|
fix test
|
2021-11-25 09:34:00 +01:00 |
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|
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a9d61526ef
|
flip rows only for hw2.0 for jungfrau
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2021-11-25 09:30:04 +01:00 |
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e7b11f3eb1
|
fix tets
|
2021-11-25 08:54:01 +01:00 |
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|
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6e49b77b08
|
updating kernel like program fpga, execute command to print which module failed, unlinking temporary file while programming bug fix
|
2021-11-03 17:17:24 +01:00 |
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|
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eff64f99f2
|
addd kernel version
|
2021-11-03 11:46:46 +01:00 |
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b39c64032d
|
clang format
|
2021-10-19 14:49:43 +02:00 |
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|
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dac60ad76d
|
added .cpp licenses
|
2021-10-15 15:47:04 +02:00 |
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cb32bfb0cd
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mythen3 works
|
2021-10-08 15:32:11 +02:00 |
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6b843097e3
|
gotthard2 passes
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2021-10-08 15:11:29 +02:00 |
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4bcc1a24f0
|
eiger passed
|
2021-10-08 15:06:09 +02:00 |
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8d309fe051
|
Merge branch 'g2speed' into fixtests
|
2021-10-08 11:31:00 +02:00 |
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|
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417bfbaf38
|
changing g_108MHz enum to g2_108MHZ (similarly 144), adding readoutspeedlist command
|
2021-10-08 11:05:25 +02:00 |
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|
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6b0e6a72df
|
changed speed to readoutspeed, added g2 speeds (108, 144)
|
2021-10-07 18:39:18 +02:00 |
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|
|
e2d7d12b3e
|
wip
|
2021-10-06 17:51:25 +02:00 |
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|
|
fb94ddec74
|
test fix
|
2021-10-04 17:18:33 +02:00 |
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|
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17e7e5058b
|
tests fix
|
2021-10-04 13:28:18 +02:00 |
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|
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cbf69f4960
|
test fix
|
2021-10-04 13:09:59 +02:00 |
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|
|
dc671e6fcf
|
udp_numdst readonly, udp_cleardst added
|
2021-09-17 16:09:57 +02:00 |
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|
|
74fde0a77c
|
entry removed and using parsing for rr
|
2021-09-15 12:11:53 +02:00 |
|
|
|
dbc541b4ea
|
test case fix for moduleid and serialnumber
|
2021-09-15 10:19:16 +02:00 |
|
Erik Frojdh
|
abf56ad643
|
WIP
|
2021-09-13 21:26:17 +02:00 |
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|
|
25d03f949e
|
partialread changed to readnrows
|
2021-08-31 16:46:49 +02:00 |
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|
|
204a4764b9
|
fixed for virtual servers rr
|
2021-08-31 11:42:17 +02:00 |
|
|
|
1d989637e9
|
udp_firstdst for jungfrau
|
2021-08-25 14:27:06 +02:00 |
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|
|
ab59f7db7b
|
added udp_numdst
|
2021-08-19 15:50:02 +02:00 |
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|
|
5790e4961b
|
wip
|
2021-08-13 17:10:46 +02:00 |
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|
|
200df88dcf
|
module id instead of serial number
|
2021-08-12 11:16:10 +02:00 |
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|
|
ff9eaaf3f3
|
serialnumber fixed to point to mod id reg
|
2021-08-11 19:30:25 +02:00 |
|
|
|
6f54402aba
|
g2: setting serialnumber allowed
|
2021-08-11 18:50:49 +02:00 |
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|
|
9a777b13bb
|
g2: dbitpipeline
|
2021-08-11 18:01:28 +02:00 |
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|
|
f0a0243233
|
fixed tests
|
2021-08-11 11:12:28 +02:00 |
|
|
|
c7293f88d0
|
done
|
2021-08-10 21:01:36 +02:00 |
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|
|
a0784d23bb
|
jungfrau: currentsource
|
2021-08-10 20:39:07 +02:00 |
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|
|
fce35e35a1
|
wip
|
2021-08-10 17:26:26 +02:00 |
|
|
|
69356cf232
|
filterresitsitor only in chipv1.1
|
2021-08-05 17:50:46 +02:00 |
|
|
|
86126c7e27
|
filter resistor in
|
2021-08-05 16:56:53 +02:00 |
|
|
|
619f3b71c1
|
flippeddataoverxaxis changed to flipRows
|
2021-08-05 14:44:25 +02:00 |
|
|
|
c5d6dd0dd4
|
flippeddatax for jungfrau server
|
2021-08-05 12:39:04 +02:00 |
|
|
|
0e5e0f346b
|
rewrote settings enums, gainmode enums
|
2021-08-04 13:07:48 +02:00 |
|
|
|
3f08d6699c
|
added test to check settings after resetdacs
|
2021-07-29 17:37:00 +02:00 |
|
|
|
9c03e83ef1
|
reset default dacs
|
2021-07-29 16:34:38 +02:00 |
|
|
|
a9663abc50
|
default dacs done
|
2021-07-29 15:56:32 +02:00 |
|
|
|
e5b17fb8e2
|
wip
|
2021-07-29 12:45:05 +02:00 |
|
|
|
de7f4489af
|
defaultdac upto detector side, settings is undefined when none given
|
2021-07-28 20:11:58 +02:00 |
|
|
|
f8b14c694d
|
jungfrau: special settings and configure chip if powered on (1.1 chip)
|
2021-07-28 13:34:32 +02:00 |
|
|
|
da996314e7
|
merge conflict
|
2021-07-22 11:15:57 +02:00 |
|
|
|
8354395f64
|
wip
|
2021-07-15 13:44:42 +02:00 |
|
