68 Commits

Author SHA1 Message Date
Dhanya Thattil
c62ce0ce6b
m3:changed str_clk (clkdiv 3) default to 166MHz (6) (#643) 2023-01-30 17:05:42 +01:00
Dhanya Thattil
3a3628c475
m3 firmware version change (#637)
* m3 firmware version change

* changed binary name to rc3
2023-01-27 10:54:45 +01:00
Dhanya Thattil
3f7c9529dd
m3: changed clk 0 1 2 to 100MHz (#636)
* m3: changed clk 0 1 2 to 100MHz

* m3:fix clk 2

* binaries in
2023-01-25 11:54:37 +01:00
91c3926eca updated fw versions for m3 to 1.4, ctb to 1.1 and moench to 0.3 2022-12-07 12:47:26 +01:00
Dhanya Thattil
2ff5291f48
hardware version (#580)
* hardware version for all dets except eiger
Co-authored-by: Erik Frojdh <erik.frojdh@gmail.com>
2022-11-24 11:24:05 +01:00
Dhanya Thattil
9f906a779e
M3clk (#548)
* m3: clock update, cannot set clk 4 and 5 anymore
* updated firmware version
2022-11-07 11:21:37 +01:00
Dhanya Thattil
46bb9bc2d7
nios temp (#557)
* fixed temp read nios

* divide for eiger and dont print
2022-10-18 15:47:23 +02:00
Dhanya Thattil
7de6f157b5
M3badchannels (#526)
* badchannels for m3 and modify for g2 (file from single and multi)

* m3: invert polarity of bit 7 and 11 signals from setmodule, allow commas in bad channel file

* badchannel file can take commas, colons and comments (also taking care of spaces at the end of channel numbers)

* tests 'badchannels' and 'Channel file reading' added, removing duplicates in badchannel list, defining macro for num counters in client side

* fix segfault when list from file is empty, 

* fix tests assertion for ctbconfig (adding message) for c++11

* fixed badchannels in m3server (clocking in trimming) 

* badchannel tests can be run from any folder (finds the file)
2022-09-01 15:30:04 +02:00
Dhanya Thattil
6bf9dbf6d3
Format (#506)
Formatted package
2022-08-05 15:39:34 +02:00
Dhanya Thattil
1fb90ab98c
M3threshold (#475)
* vicin default changed to 800, only setting vthx directly allows to set dac even if counter disabled, else disable counter, setallthresholdenergy if an energy is -1, get module value, fix that reg was repaced by isettings

* vth3 disabled for interpolation enable, interpolation disable sets counter mask to what it was before (updating old mask whn setting counter mask except for setting all counters for interpolation enable) and enabling vth3 if counter was enabled

* refactor and test for previous commit

* pump probe only has vth2 enabled, handles both pump probe mode and interpolation mode as well

* wip

* refactored pump probe and interpolation and added to setmodule

* check dacs and trimbits out of range for setmodule (not just threshold)

* binaries in

* m3: pump probe and interpolation mutually exclusive

* minor
2022-06-07 16:55:33 +02:00
abdc755dc2 fix for m3 crash 2022-02-03 09:18:47 +01:00
340d708b12 updated m3 kernel version 2021-11-02 17:07:55 +01:00
203d6465a1 clang and redoing copy detector server to have a soft link and put that in respawning for blackfin servers 2021-10-18 17:17:56 +02:00
4de7bb51ed updated all .h files with license notice and copyright notice 2021-10-14 18:10:56 +02:00
a17b7b1778 m3:connected module id 2021-09-15 11:06:39 +02:00
a9663abc50 default dacs done 2021-07-29 15:56:32 +02:00
122f0a4a87 merge from 5.2.0-rc 2021-07-27 17:08:59 +02:00
1e441af30b g2: allowing module id values for master and slave modules 2021-07-27 17:02:20 +02:00
Erik Frojdh
7004f43a9a Merge branch 'developer' into my3regs 2021-03-23 11:44:52 +01:00
Erik Fröjdh
2f2fe4dd47
Release of 5.1.0 (#237)
* Setting pattern from memory (#218)

* ToString accepts c-style arrays

* fixed patwait time bug in validation

* Introduced pattern class

* compile for servers too

* Python binding for Pattern

* added scanParameters in Python

* slsReceiver: avoid potential memory leak around Implementation::generalData

* additional constructors for scanPrameters in python

* bugfix: avoid potentital memory leak in receiver if called outside constructor context

* added scanParameters in Python

* additional constructors for scanPrameters in python

* M3defaultpattern (#227)

* default pattern for m3 and moench including Python bindings

* M3settings (#228)

* some changes to compile on RH7 and in the server to load the default chip status register at startup

* Updated mythen3DeectorServer_developer executable with correct initialization at startup

Co-authored-by: Erik Frojdh <erik.frojdh@gmail.com>
Co-authored-by: Anna Bergamaschi <anna.bergamaschi@psi.ch>

* Pattern.h as a public header files (#229)

* fixed buffer overflow but caused by using global instead of local enum

* replacing out of range trimbits with edge values

* replacing dac values that are out of range after interpolation

* updated pybind11 to 2.6.2

* Mythen3 improved synchronization (#231)

Disabling scans for multi module Mythen3, since there is no feedback of the detectors being ready
startDetector first starts the slaves then the master
acquire firs calls startDetector for the slaves then acquire on the master
getMaster to read back from hardware which one is master

* New server for JF to go with the new FW (#232)

* Modified Jungfrau speed settings for HW1.0 - FW fix version 1.1.1, compilation date 210218

* Corrected bug. DBIT clk phase is implemented in both HW version 1.0 and 2.0. Previous version did not update the DBIT phase shift on the configuration of a speed.

* fix for m3 scan with single module

* m3 fw version

* m3 server

* bugfix for bottom when setting quad

* new strategy for finding zmq based on cppzmq



Co-authored-by: Dhanya Thattil <dhanya.thattil@psi.ch>
Co-authored-by: Dhanya Thattil <33750417+thattil@users.noreply.github.com>
Co-authored-by: Alejandro Homs Puron <ahoms@esrf.fr>
Co-authored-by: Anna Bergamaschi <anna.bergamaschi@psi.ch>
Co-authored-by: Xiaoqiang Wang <xiaoqiangwang@gmail.com>
Co-authored-by: lopez_c <carlos.lopez-cuenca@psi.ch>
2021-03-22 14:43:11 +01:00
63259ec5c8 Modified my3 functions for the pattern generator and moved to separate file; created loadPattern function - but should still be used in readDefaultPattern 2021-02-26 16:53:30 +01:00
Dhanya Thattil
f9f50f1d84
M3settings (#228)
* added temp m3 settings files

* renames settings noise to trim

* get threshold for M3

* some changes to compile on RH7 and in the server to load the default chip status register at startup

* Updated mythen3DeectorServer_developer executable with correct initialization at startup

Co-authored-by: Erik Frojdh <erik.frojdh@gmail.com>
Co-authored-by: Anna Bergamaschi <anna.bergamaschi@psi.ch>
2021-01-14 12:34:13 +01:00
Erik Fröjdh
a15d8dd30a
Moving headers into include/sls (#212) 2020-11-02 16:05:28 +01:00
e364fbcf32 m3: changed run clk div to 10, change run clkdiv to 40 while trimming, set default pipeline adif reg 2020-10-09 16:52:24 +02:00
91efecd4ca servers: updated fw-sw api version check error message, m3 and g2: updated min fw version 2020-10-02 11:17:11 +02:00
a9d1a78662 m3:smp_clk (timing rxr) changed back to clk div 5 2020-09-09 15:55:13 +02:00
bfbfe204f4 m3: default clocks changed 2020-09-08 17:31:44 +02:00
20a959bf61 update mode to skip firmware checks and setupDetector, kernel check added to m3and g2 2020-09-08 15:08:45 +02:00
00978a52c8 added smp_clk, changed rdo vco freq from 1.25GHz to 1GHz, changed rdo clock dividers 2020-09-01 12:06:39 +02:00
eeb386fef5 mythen3: txndelay frame added 2020-08-18 15:27:30 +02:00
0514f00552 m3: update deserializers except for deserializer reg 2020-08-03 17:23:04 +02:00
Dhanya Thattil
7492f7dbfa
m3: numpackets to 2 or 20 depending on ten giga enable (#123) 2020-07-30 15:02:33 +02:00
28fb1023fa mythen3: rename default pattern txt and move to inst dir 2020-07-20 17:18:59 +02:00
b7cb341ee3 dr 2020-07-17 17:33:43 +02:00
4a1943216b default pattern file for mythen3 2020-07-07 15:50:32 +02:00
9d3bbc0a68 WIP 2020-06-22 15:02:28 +02:00
d5ae9a22f4 mythen3: changed system vco from 1.25GHz to 1GHz and hence the sytem clock dividers defaults 2020-06-16 15:00:02 +02:00
Dhanya Thattil
f5160b0978
exposing receiver thread ids to client (#102)
* exposing receiver thread ids to client

Co-authored-by: Erik Frojdh <erik.frojdh@gmail.com>
2020-06-09 16:18:37 +02:00
8aa7144252 mythen3: fix of external signals to not allow master output inversion, but can edge detect not configurable, and default dout pulse length 2020-05-28 13:09:09 +02:00
44a88893ba mythen3: hv soft max uptdated to 500v 2020-05-26 14:58:41 +02:00
d71e40729a external signals 2020-05-20 17:05:42 +02:00
cd90f09a30 WIP 2020-05-19 18:24:32 +02:00
1a75170eed mythen3: set trimbits (not settings, threshold yet), set all trimbits 2020-05-07 16:04:30 +02:00
671cf45fd7 format slsdetectorservers 2020-05-05 15:23:11 +02:00
86b39853a3 gotthard2, mythen3: making them clkdivider dependant and not clkfrequency, binaries not loaded yet 2020-04-28 17:04:57 +02:00
02b367ffe8 mythen3 and gotthard2: updated clocks 2020-02-24 16:50:47 +01:00
8cbf3c62a9 merge from developer 2020-01-22 17:30:13 +01:00
981b13494c mythen3: virtual server, connected timing mode, row and col in header, included pattern bit and mask 2020-01-21 18:16:27 +01:00
e8bdf5a505 gotthard2: updated register map; powerchip checking detector type; internal and external period, frames, exptime; set/get delay, get actualtime, measurement, framesfromstart enabled; which detector comment updated in cmdproxy, detector and slsdetector 2020-01-16 15:33:35 +01:00
Dhanya Thattil
de53747ddd Counters (#71)
* mythen3: adding counters mask, firmware still takes only number of counters for now

* mythen3: checking if module attached before powering on chip

* bug fix: loop inital declaration not allowed in c

* fix scope eiger test

* mythen3: renamed setCounters to setCounterMask and getCounterMask in API

* mythen3 replacing counting bits with popcount

Co-authored-by: Erik Fröjdh <erik.frojdh@gmail.com>
2020-01-14 17:40:46 +01:00