Dhanya Thattil
3f19f29c9e
G2ContTrigger ( #188 )
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* g2: setting #frames to 1 and period to 0 for cont trigger, extra frame reg is set to #frames for cont auto and #trigger for cont trigger
2020-09-24 11:59:11 +02:00
5214c0f1a4
binaries in
2020-09-10 18:43:26 +02:00
88fe306902
binaries in
2020-09-10 16:23:29 +02:00
80b053eb10
binaries resolved, merge conflict from developer
2020-09-10 10:19:34 +02:00
Dhanya Thattil
3cd4f3897b
M3: software trigger ( #175 )
2020-09-10 10:15:45 +02:00
52303daffd
binaries in
2020-09-09 16:44:23 +02:00
a9d1a78662
m3:smp_clk (timing rxr) changed back to clk div 5
2020-09-09 15:55:13 +02:00
3cf2160a2d
binaries in
2020-09-09 15:25:48 +02:00
b33fdf4462
merge conflict fixed and merged with developer
2020-09-09 12:31:36 +02:00
6c8443f09e
binaries in
2020-09-09 12:14:38 +02:00
97687f0f6d
binary in
2020-09-08 17:33:06 +02:00
87bad38f80
binary in
2020-09-08 15:46:32 +02:00
e1e04ee755
binaries in
2020-09-08 15:18:07 +02:00
aecde086a0
binaries in
2020-09-08 12:16:41 +02:00
f26d8e514b
merged with g2continuous
2020-09-08 08:46:37 +02:00
0b9ff70244
binaries in
2020-09-08 08:25:24 +02:00
891b8dbd2c
mythen3: wrong hardware version number, so it didnt reboot after programfpga
2020-09-03 17:04:58 +02:00
00978a52c8
added smp_clk, changed rdo vco freq from 1.25GHz to 1GHz, changed rdo clock dividers
2020-09-01 12:06:39 +02:00
7ea86dec43
m3 binaries in
2020-08-18 15:28:30 +02:00
27b2a607c8
binaries in
2020-08-10 12:05:37 +02:00
bbf8ab4b88
binary in
2020-08-05 09:49:13 +02:00
321ed13659
merge from developer
2020-08-04 17:43:38 +02:00
f6172f9b9e
binary in
2020-08-04 17:36:49 +02:00
bb3951c201
binaries in
2020-08-04 16:57:06 +02:00
d25f9093d5
binary in
2020-08-04 12:02:37 +02:00
f358492e09
all binaries in
2020-07-29 16:53:21 +02:00
54ad92a2bf
binarires in
2020-07-29 13:26:55 +02:00
Dhanya Thattil
ad297e9c51
Readlink ( #117 )
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* gotthard config file path using readlink
* gotthard2
* eiger
* eieger, mnythen3, moench
* binaries in
* moved readlink to a common function
* binaries in
2020-07-23 12:17:46 +02:00
b46809e1c0
binaries in
2020-07-20 17:36:55 +02:00
918da2402f
binaries in
2020-07-17 19:06:30 +02:00
2d68b61f00
binaries recompiled
2020-07-17 12:59:37 +02:00
ae9499047b
powerpc and nios binaries in
2020-07-16 16:36:49 +02:00
293fda0c7a
mythen3, gotthard2: bug fix- changing wrong pll phases when changing frequency
2020-07-13 15:47:43 +02:00
42b7f6fa7c
binary in
2020-07-08 11:35:46 +02:00
28b3fb4101
binaries
2020-07-03 17:15:24 +02:00
7c48ef8931
binaries and fix
2020-07-02 17:15:24 +02:00
0dc062e6d3
binaries
2020-07-02 16:41:03 +02:00
a228ae0773
binaries
2020-07-02 16:38:00 +02:00
c5a9ff3024
binaries in
2020-07-02 15:53:57 +02:00
3156e6f50e
binaries
2020-07-01 13:13:52 +02:00
e571f7bb3e
WIP
2020-07-01 09:10:49 +02:00
aacc61b058
WIP
2020-06-30 17:11:51 +02:00
279986d77c
WIP
2020-06-30 12:09:23 +02:00
f1cbf49449
binaries in
2020-06-30 09:06:15 +02:00
4cbe354396
pattern word prints every 10 for pattern file
2020-06-23 12:47:06 +02:00
ae88af2a72
fix
2020-06-23 12:10:40 +02:00
5c42792580
binaries in
2020-06-23 11:00:51 +02:00
f14c2d06a5
binaries in
2020-06-18 17:41:32 +02:00
8adddfb083
binaries in
2020-06-18 12:42:53 +02:00
7609a2bda4
mythen3: timers based on run clk and not on sync clk
2020-06-16 16:47:03 +02:00
