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3486137de3
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bfin warnings fixed
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2019-11-27 18:22:33 +01:00 |
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9455a5fba1
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ctb: adcenable10g included, 10g readout enables included
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2019-11-27 17:28:57 +01:00 |
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f299a34e59
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ctb server binary update
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2019-11-27 11:31:30 +01:00 |
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9e8a874e39
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rxr bug fix: update shm when updating rxr
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2019-11-27 11:12:31 +01:00 |
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6b391a34dc
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gotthard2: bug fix adconfiguration initialization
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2019-11-25 14:14:05 +01:00 |
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94382c1ece
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m3 and g2: while setting clock freq, change phase only if there is a change in phase (removing more printouts, will still only set if needed )
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2019-11-25 10:54:30 +01:00 |
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c4675da0c3
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m3: reset fixed
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2019-11-22 16:40:43 +01:00 |
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d07873ee39
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mythen3 and gotthard2: wait request not needed, reset to be implemented
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2019-11-22 11:29:24 +01:00 |
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f8df11886a
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ctb: change in phase done in degrees (phase reset due to change in frequency)
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2019-11-21 15:08:38 +01:00 |
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d976c9fcf9
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gotthard2: phase direction like mythen3
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2019-11-21 14:41:54 +01:00 |
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955bc74a91
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mythen3: change vco freq to 1.25GHz
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2019-11-21 13:38:54 +01:00 |
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781e8fc67f
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mythen3: workaround for busy signal
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2019-11-20 11:57:14 +01:00 |
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1cea6af590
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mythen3, gotthard2: change phase, change freq bugfix
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2019-11-19 17:57:28 +01:00 |
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dfc886a65b
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mythen3 gui
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2019-11-18 17:57:19 +01:00 |
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a62d6a2fb8
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gotthard2: veto reference, better code for byte aligment in server
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2019-11-15 11:58:23 +01:00 |
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5518531620
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gotthard2: veto reference
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2019-11-14 19:01:10 +01:00 |
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28a5aa8342
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injectchannel WIP
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2019-11-13 15:11:11 +01:00 |
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72ac2745ea
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gotthard2: server fix enum for onchip dac
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2019-11-12 12:11:52 +01:00 |
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2fff9f5bfe
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merge
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2019-11-11 18:03:13 +01:00 |
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90c34e4942
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gotthard2, dacs and onchip dacs from config file
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2019-11-11 18:02:08 +01:00 |
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bb26b993ea
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servers, firmware check message to init message, minor
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2019-11-11 12:00:04 +01:00 |
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2123fb47a5
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mythen3: config reg enable all counters, dr
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2019-11-11 10:41:42 +01:00 |
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38ad5d7931
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mythen3 rxr
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2019-11-08 18:11:27 +01:00 |
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d7e2ab8ec4
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gotthard2: on chip dacs
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2019-11-08 17:09:57 +01:00 |
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a92d931a8f
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mythen3 frequency fixes
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2019-11-07 14:35:13 +01:00 |
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615b3b2557
|
WIP
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2019-11-06 19:07:00 +01:00 |
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1797d39216
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updated mythen3 to configure phase, freq, delay left, period left, actual time, measurement time, framesfrom start and othe register mappings
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2019-11-06 18:58:22 +01:00 |
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0f9fd5cd73
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rename of clkdivider to clkfrequency in servers
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2019-11-06 16:58:34 +01:00 |
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73b5c3ac57
|
merge
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2019-11-06 16:46:00 +01:00 |
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18b8720c17
|
separated parameters and versions
|
2019-11-06 16:43:59 +01:00 |
|
Marie Andrae
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7de9401bc7
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powerchip for mythen3
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2019-11-06 11:50:09 +01:00 |
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567e821569
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updated ieger server
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2019-11-05 18:52:51 +01:00 |
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1f64d2a4e2
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speed separated
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2019-11-05 18:50:35 +01:00 |
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031241ae28
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timer split up
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2019-11-04 16:40:11 +01:00 |
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6c5c4f00b3
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mythen3 calc checksum
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2019-10-31 12:31:51 +01:00 |
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ba9a0c7917
|
removed unused multi functions
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2019-10-30 18:20:16 +01:00 |
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11ea071543
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adcinvert for jungfrau, gui for jungfrau dacs
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2019-10-30 12:28:51 +01:00 |
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82570bc084
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daclist and dacvalues
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2019-10-30 11:09:34 +01:00 |
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fe467cdf70
|
jungfrau dacs named
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2019-10-29 18:11:16 +01:00 |
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aa8610fb04
|
WIP
|
2019-10-29 10:11:36 +01:00 |
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798f221764
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WIP
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2019-10-29 10:07:07 +01:00 |
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f4a0780b51
|
patloops done
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2019-10-24 18:59:23 +02:00 |
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f73a15e786
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tests made to pass ctb
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2019-10-24 11:32:58 +02:00 |
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fa84d17a19
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gotthard tests passed
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2019-10-22 17:07:38 +02:00 |
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8c6da7da1b
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jungfrau storage cell bug fix
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2019-10-22 13:38:17 +02:00 |
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f2fc187f13
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better testing for eiger
|
2019-10-21 15:10:31 +02:00 |
|
Dhanya Thattil
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995f0924e5
|
Commandline (#66)
* WIP
* WIP
* removed status to string from defs
* WIP
* WIP
* WIP removed unused functions in multi
* WIP
* print hex in a terrible way
* WIP, loadconfig error
* WIP, type to string
* WIP
* fix to conversion
* WIP, hostname doesnt work
* WIP
* WIP
* WIP
* WIP, threshold
* WIP, threshold
* WIP
* WIP, triggers
* WIP, cycles to triggers
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* rx_udsocksize fx, WIP
* WIP
* WIP
* WIP
* file index (64 bit), WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* merge
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* New python mod
|
2019-10-21 10:29:06 +02:00 |
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|
be50344b45
|
set clock divider, phase and get clock freq for gotthard2, priliminary
|
2019-10-17 16:39:41 +02:00 |
|
Marie Andrä
|
9b4fc02b0e
|
start/stop statemachine for my3 (#68)
* start/stop statemachine for my3
* runStatus, readFrame, runBusy (use CONTROL_REG) for mythen3
* registers for Pavel
* change dac names Mythen3
|
2019-10-09 13:52:07 +02:00 |
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|
|
b109ea8d7d
|
jungfrau vref_prech, dac enum similar to mainenum
|
2019-10-08 18:00:22 +02:00 |
|
