6e47f0b7f7
merge resolved
2020-01-20 11:36:35 +01:00
3c891495db
mythen3: bug fix detector type
2020-01-20 11:32:02 +01:00
e8bdf5a505
gotthard2: updated register map; powerchip checking detector type; internal and external period, frames, exptime; set/get delay, get actualtime, measurement, framesfromstart enabled; which detector comment updated in cmdproxy, detector and slsdetector
2020-01-16 15:33:35 +01:00
Dhanya Thattil
de53747ddd
Counters ( #71 )
...
* mythen3: adding counters mask, firmware still takes only number of counters for now
* mythen3: checking if module attached before powering on chip
* bug fix: loop inital declaration not allowed in c
* fix scope eiger test
* mythen3: renamed setCounters to setCounterMask and getCounterMask in API
* mythen3 replacing counting bits with popcount
Co-authored-by: Erik Fröjdh <erik.frojdh@gmail.com>
2020-01-14 17:40:46 +01:00
7b31fbc002
eiger virtual server bug fix: increasing subdeadtime
2020-01-13 14:18:43 +01:00
28f8a76dcc
updated binaries
2020-01-10 09:05:26 +01:00
086cbacd84
mythen3: connected busy signal insttead of timer
2019-12-10 11:03:27 +01:00
af9b25fd67
eiger: validate trimval range
2019-12-10 10:32:28 +01:00
504fc2d095
ctb: validate asampes and dsamples > 0 for romode; client: exception caught in acquire to stop receiver and clear busy flag
2019-12-10 10:25:14 +01:00
5cf1502287
ctb bug fix: 10g adc enable mask
2019-12-09 11:30:54 +01:00
2ece6b945e
rxr: warnings shouldnt throw exception
2019-11-29 11:09:41 +01:00
3486137de3
bfin warnings fixed
2019-11-27 18:22:33 +01:00
9455a5fba1
ctb: adcenable10g included, 10g readout enables included
2019-11-27 17:28:57 +01:00
f299a34e59
ctb server binary update
2019-11-27 11:31:30 +01:00
6b391a34dc
gotthard2: bug fix adconfiguration initialization
2019-11-25 14:14:05 +01:00
94382c1ece
m3 and g2: while setting clock freq, change phase only if there is a change in phase (removing more printouts, will still only set if needed )
2019-11-25 10:54:30 +01:00
a95ab1e13e
servers: default compile not update versionign
2019-11-22 17:23:07 +01:00
c4675da0c3
m3: reset fixed
2019-11-22 16:40:43 +01:00
ba008db29a
m3 ang g2: reset not yet imple
2019-11-22 11:54:45 +01:00
950096daf9
m3 ang g2: reset not yet imple
2019-11-22 11:54:30 +01:00
d07873ee39
mythen3 and gotthard2: wait request not needed, reset to be implemented
2019-11-22 11:29:24 +01:00
f8df11886a
ctb: change in phase done in degrees (phase reset due to change in frequency)
2019-11-21 15:08:38 +01:00
d976c9fcf9
gotthard2: phase direction like mythen3
2019-11-21 14:41:54 +01:00
c4ae32b216
mythen3: setting clk frequecy and phase shifts work
2019-11-21 14:36:37 +01:00
fea94b15d5
mythen3:forgot binary
2019-11-21 13:48:39 +01:00
955bc74a91
mythen3: change vco freq to 1.25GHz
2019-11-21 13:38:54 +01:00
781e8fc67f
mythen3: workaround for busy signal
2019-11-20 11:57:14 +01:00
1cea6af590
mythen3, gotthard2: change phase, change freq bugfix
2019-11-19 17:57:28 +01:00
dfc886a65b
mythen3 gui
2019-11-18 17:57:19 +01:00
6a27207875
gotthard2: vetoref, burstmode
2019-11-15 18:59:27 +01:00
a62d6a2fb8
gotthard2: veto reference, better code for byte aligment in server
2019-11-15 11:58:23 +01:00
5518531620
gotthard2: veto reference
2019-11-14 19:01:10 +01:00
21d23be522
gotthard2: inejct channel done
2019-11-13 16:49:35 +01:00
28a5aa8342
injectchannel WIP
2019-11-13 15:11:11 +01:00
72ac2745ea
gotthard2: server fix enum for onchip dac
2019-11-12 12:11:52 +01:00
206041989f
mythen3, reading dr back fix
2019-11-11 18:33:59 +01:00
2fff9f5bfe
merge
2019-11-11 18:03:13 +01:00
90c34e4942
gotthard2, dacs and onchip dacs from config file
2019-11-11 18:02:08 +01:00
bb26b993ea
servers, firmware check message to init message, minor
2019-11-11 12:00:04 +01:00
Marie Andrae
f53d260202
mythen3: change vph and vpl
2019-11-11 11:40:06 +01:00
2123fb47a5
mythen3: config reg enable all counters, dr
2019-11-11 10:41:42 +01:00
38ad5d7931
mythen3 rxr
2019-11-08 18:11:27 +01:00
aaeaeab576
gotthard2 on chip dacs: -1 should set for all chips
2019-11-08 17:20:47 +01:00
03ec2c53ab
WIP
2019-11-08 17:10:28 +01:00
d7e2ab8ec4
gotthard2: on chip dacs
2019-11-08 17:09:57 +01:00
a92d931a8f
mythen3 frequency fixes
2019-11-07 14:35:13 +01:00
615b3b2557
WIP
2019-11-06 19:07:00 +01:00
1797d39216
updated mythen3 to configure phase, freq, delay left, period left, actual time, measurement time, framesfrom start and othe register mappings
2019-11-06 18:58:22 +01:00
0f9fd5cd73
rename of clkdivider to clkfrequency in servers
2019-11-06 16:58:34 +01:00
73b5c3ac57
merge
2019-11-06 16:46:00 +01:00
