5 Commits

Author	SHA1	Message	Date
Dhanya Thattil	969551ae37	program fpga made parallel	2019-03-29 17:59:06 +01:00
Dhanya Thattil	c7c52c63cd	ctb & moench: phase fix for absolute within limits, option to set as degrees and get max phase shift, bug fix for eiger with implementation of 2 udp interface	2019-03-27 12:25:38 +01:00
Dhanya Thattil	7cd5bc8b2d	jungfrau: switching between 2 and 1 interface, implementation for server required when firmware done	2019-03-26 15:00:19 +01:00
Erik Frojdh	83e43b1bcf	format ColumnLimit changed to 100	2019-03-20 17:31:19 +01:00
Erik Frojdh	4b2c6af4f5	reorganizing of slsDetectorSoftware	2019-03-20 17:07:02 +01:00