Commit Graph
299 Commits
Author SHA1 Message Date
maliakal_d 615b3b2557 WIP 2019-11-06 19:07:00 +01:00
maliakal_d 1797d39216 updated mythen3 to configure phase, freq, delay left, period left, actual time, measurement time, framesfrom start and othe register mappings 2019-11-06 18:58:22 +01:00
maliakal_d 0f9fd5cd73 rename of clkdivider to clkfrequency in servers 2019-11-06 16:58:34 +01:00
maliakal_d 73b5c3ac57 merge 2019-11-06 16:46:00 +01:00
maliakal_d 18b8720c17 separated parameters and versions 2019-11-06 16:43:59 +01:00
Marie Andrae 7de9401bc7 powerchip for mythen3 2019-11-06 11:50:09 +01:00
maliakal_d 705ddb7f42 WIP 2019-11-06 11:11:57 +01:00
maliakal_d cd5d327988 virtual servers updated 2019-11-06 11:09:48 +01:00
maliakal_d c3180737ed fixed jungfau virtual server as well 2019-11-06 11:05:02 +01:00
maliakal_d ba37a51858 eiger virtual server exptime fixed 2019-11-06 10:54:33 +01:00
maliakal_d 567e821569 updated ieger server 2019-11-05 18:52:51 +01:00
maliakal_d 1f64d2a4e2 speed separated 2019-11-05 18:50:35 +01:00
maliakal_d 96d64778ee eiger virtual server bug fix, detectorip and detectormac of hostpc 2019-11-05 14:46:58 +01:00
maliakal_d 40572b6b23 WIP 2019-11-04 16:48:40 +01:00
maliakal_d 031241ae28 timer split up 2019-11-04 16:40:11 +01:00
maliakal_d f9fff97f8a mythen3 register mix up 2019-10-31 14:48:53 +01:00
maliakal_d 6c5c4f00b3 mythen3 calc checksum 2019-10-31 12:31:51 +01:00
maliakal_d ba9a0c7917 removed unused multi functions 2019-10-30 18:20:16 +01:00
maliakal_d 11ea071543 adcinvert for jungfrau, gui for jungfrau dacs 2019-10-30 12:28:51 +01:00
maliakal_d 82570bc084 daclist and dacvalues 2019-10-30 11:09:34 +01:00
maliakal_d fe467cdf70 jungfrau dacs named 2019-10-29 18:11:16 +01:00
maliakal_d aa8610fb04 WIP 2019-10-29 10:11:36 +01:00
maliakal_d 798f221764 WIP 2019-10-29 10:07:07 +01:00
maliakal_d f4a0780b51 patloops done 2019-10-24 18:59:23 +02:00
maliakal_d f73a15e786 tests made to pass ctb 2019-10-24 11:32:58 +02:00
maliakal_d fa84d17a19 gotthard tests passed 2019-10-22 17:07:38 +02:00
maliakal_d 8006043a97 bug fixes for tests 2019-10-22 15:46:28 +02:00
maliakal_d 45012df95b jungfrau registers updated 2019-10-22 14:02:52 +02:00
maliakal_d 8c6da7da1b jungfrau storage cell bug fix 2019-10-22 13:38:17 +02:00
maliakal_d f2fc187f13 better testing for eiger 2019-10-21 15:10:31 +02:00
Dhanya ThattilandGitHub 995f0924e5 Commandline (#66)
* WIP

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* removed status to string from defs

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* WIP removed unused functions in multi

* WIP

* print hex in a terrible way

* WIP, loadconfig error

* WIP, type to string

* WIP

* fix to conversion

* WIP, hostname doesnt work

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* WIP, threshold

* WIP, threshold

* WIP

* WIP, triggers

* WIP, cycles to triggers

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* rx_udsocksize fx, WIP

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* file index (64 bit), WIP

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* merge

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* New python mod
2019-10-21 10:29:06 +02:00
maliakal_d df4f37efc6 gotthard2, change clock, remember in degrees, and max clock divider is 512 2019-10-17 18:29:57 +02:00
maliakal_d e16212bd23 tests for clk for gotthard2 2019-10-17 16:51:40 +02:00
maliakal_d be50344b45 set clock divider, phase and get clock freq for gotthard2, priliminary 2019-10-17 16:39:41 +02:00
Marie AndräandDhanya Thattil 9b4fc02b0e start/stop statemachine for my3 (#68)
* start/stop statemachine for my3

* runStatus, readFrame, runBusy (use CONTROL_REG) for mythen3

* registers for Pavel

* change dac names Mythen3
2019-10-09 13:52:07 +02:00
maliakal_d b109ea8d7d jungfrau vref_prech, dac enum similar to mainenum 2019-10-08 18:00:22 +02:00
maliakal_d cfd3680176 gotthard2 dacs 2019-10-08 17:10:36 +02:00
maliakal_d 030cfacc9b WIP 2019-10-08 10:57:07 +02:00
Marie AndräandDhanya Thattil 5f94b5c246 Dac (#67)
* dac WIP

* dacs WIP

* DACs are working with names

* namechanges of vrfsh->vshaper, vrfshnpol->vshaperneg

* pattern for MY3, configure MAC for MY3
2019-10-07 12:13:25 +02:00
maliakal_d 0f99dd141e gotthard 2 server test bus 2019-10-01 17:34:52 +02:00
maliakal_d b3ff825ce8 updated gotthard2 api etc 2019-10-01 16:26:42 +02:00
maliakal_d 2a40c7f48e recompiled all servers 2019-09-30 14:54:31 +02:00
Dhanya ThattilandGitHub ca054626e6 Removeudpcache (#65)
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* solved eiger 1-10g issue

* some fixes for remove udp cache to work

* bug fix virtual

* removed special handling of rx_udpip
2019-09-30 14:46:25 +02:00
Marie AndräandDhanya Thattil 6e6fcec698 MY3.0:read and write Registers, frames, cycles, delay (#64)
* MY3.0:read and write Registers, frames, cycles, delay

* write pattern seems to work

* done all corrections. added default clks: run_clk=125MHz, tick_clk=20MHz (fix), sampling_clk=80MHz (from Carlos)

* clk check for aquistition time

* clk check for aquistition time

* Update slsDetectorServer_defs.h

* Update slsDetectorFunctionList.c
2019-09-30 14:36:33 +02:00
maliakal_d 3d52a2f169 minor chnages 2019-09-27 16:39:46 +02:00
maliakal_d 8a4a6c7004 hvdac location change 2019-09-27 16:17:01 +02:00
maliakal_d 288b59d292 gotthard2 changes for first firmware version 2019-09-26 14:10:11 +02:00
Erik Frojdh 27d223d199 testing 2019-09-19 12:12:25 +02:00
maliakal_d 21ce0055b2 gotthard2: soft limit to list 2019-09-03 09:41:54 +02:00
Marie AndräandDhanya Thattil 4b987abf41 Niosmarie (#63)
* HV for Mythen3 server

* HV for mythen3 server

* corrected upstreams

* missing endif
2019-09-03 09:36:02 +02:00