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speed separated

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This commit is contained in:
maliakal_d
2019-11-05 18:50:35 +01:00
parent 96d64778ee
commit 1f64d2a4e2
29 changed files with 830 additions and 714 deletions
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slsDetectorServers/ctbDetectorServer/bin/ctbDetectorServer_developer
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193
slsDetectorServers/ctbDetectorServer/slsDetectorFunctionList.c
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@ -750,70 +750,7 @@ int setExternalSampling(int val) {
return ((bus_r(addr) & DBIT_EXT_TRG_OPRTN_MD_MSK) >> DBIT_EXT_TRG_OPRTN_MD_OFST);
}
/* parameters - speed, readout */
void setSpeed(enum speedVariable ind, int val, int mode) {
switch(ind) {
case ADC_PHASE:
FILE_LOG(logINFOBLUE, ("Configuring ADC Phase\n"));
configurePhase(ADC_CLK, val, mode);
break;
case DBIT_PHASE:
FILE_LOG(logINFOBLUE, ("Configuring Dbit Phase\n"));
configurePhase(DBIT_CLK, val, mode);
break;
case ADC_CLOCK:
FILE_LOG(logINFOBLUE, ("Configuring ADC Clock\n"));
configureFrequency(ADC_CLK, val);
configureSyncFrequency(ADC_CLK);
break;
case DBIT_CLOCK:
FILE_LOG(logINFOBLUE, ("Configuring Dbit Clock\n"));
configureFrequency(DBIT_CLK, val);
configureSyncFrequency(DBIT_CLK);
break;
case ADC_PIPELINE:
setAdcOffsetRegister(1, val);
break;
case DBIT_PIPELINE:
setAdcOffsetRegister(0, val);
break;
case CLOCK_DIVIDER:
FILE_LOG(logINFOBLUE, ("Configuring Run Clock\n"));
configureFrequency(RUN_CLK, val);
configureSyncFrequency(RUN_CLK);
break;
default:
return;
}
}
int getSpeed(enum speedVariable ind, int mode) {
switch(ind) {
case ADC_PHASE:
return getPhase(ADC_CLK, mode);
case DBIT_PHASE:
return getPhase(DBIT_CLK, mode);
case MAX_ADC_PHASE_SHIFT:
return getMaxPhase(ADC_CLK);
case MAX_DBIT_PHASE_SHIFT:
return getMaxPhase(DBIT_CLK);
case ADC_CLOCK:
return getFrequency(ADC_CLK);
case DBIT_CLOCK:
return getFrequency(DBIT_CLK);
case SYNC_CLOCK:
return getFrequency(SYNC_CLK);
case CLOCK_DIVIDER:
return getFrequency(RUN_CLK);
case ADC_PIPELINE:
return getAdcOffsetRegister(1);
case DBIT_PIPELINE:
return getAdcOffsetRegister(0);
default:
return -1;
}
}
/* parameters - readout */
int setReadoutMode(enum readoutMode mode) {
uint32_t addr = CONFIG_REG;
@ -1613,22 +1550,24 @@ int enableTenGigabitEthernet(int val) {
/* ctb specific - configure frequency, phase, pll */
// ind can only be ADC_CLK or DBIT_CLK
void configurePhase(enum CLKINDEX ind, int val, int degrees) {
char clock_names[4][10]={"run_clk","adc_clk", "sync_clk", "dbit_clk"};
int setPhase(enum CLKINDEX ind, int val, int degrees) {
if (ind != ADC_CLK && ind != DBIT_CLK) {
FILE_LOG(logERROR, ("Unknown clock index %d to set phase\n", ind));
return FAIL;
}
char* clock_names[] = {CLK_NAMES};
FILE_LOG(logINFO, ("Setting %s clock (%d) phase to %d %s\n", clock_names[ind], ind, val, degrees == 0 ? "" : "degrees"));
int maxShift = getMaxPhase(ind);
// validation
if (degrees && (val < 0 || val > 359)) {
FILE_LOG(logERROR, ("\tPhase provided for C%d(%s) outside limits (0 - 359°C)\n", ind, clock_names[ind]));
return;
FILE_LOG(logERROR, ("\tPhase outside limits (0 - 359°C)\n"));
return FAIL;
}
if (!degrees && (val < 0 || val > maxShift - 1)) {
FILE_LOG(logERROR, ("\tPhase provided for C%d(%s) outside limits (0 - %d phase shifts)\n", ind, clock_names[ind], maxShift - 1));
return;
FILE_LOG(logERROR, ("\tPhase outside limits (0 - %d phase shifts)\n", maxShift - 1));
return FAIL;
}
FILE_LOG(logDEBUG1, ("\tConfiguring Phase of C%d(%s) to %d (degree mode: %d)\n", ind, clock_names[ind], val, degrees));
int valShift = val;
// convert to phase shift
if (degrees) {
@ -1642,9 +1581,9 @@ void configurePhase(enum CLKINDEX ind, int val, int degrees) {
// same phase
if (!relativePhase) {
FILE_LOG(logINFO, ("\tNothing to do in Phase Shift\n"));
return;
return OK;
}
FILE_LOG(logINFOBLUE, ("\tConfiguring Phase of C%d(%s) to %d (degree mode: %d)\n", ind, clock_names[ind], val, degrees));
FILE_LOG(logINFOBLUE, ("Configuring Phase\n"));
int phase = 0;
if (relativePhase > 0) {
@ -1657,9 +1596,14 @@ void configurePhase(enum CLKINDEX ind, int val, int degrees) {
ALTERA_PLL_SetPhaseShift(phase, (int)ind, 0);
clkPhase[ind] = valShift;
return OK;
}
int getPhase(enum CLKINDEX ind, int degrees) {
if (ind != ADC_CLK && ind != DBIT_CLK) {
FILE_LOG(logERROR, ("Unknown clock index %d to get phase\n", ind));
return -1;
}
if (!degrees)
return clkPhase[ind];
// convert back to degrees
@ -1669,32 +1613,29 @@ int getPhase(enum CLKINDEX ind, int degrees) {
}
int getMaxPhase(enum CLKINDEX ind) {
if (ind != ADC_CLK && ind != DBIT_CLK) {
FILE_LOG(logERROR, ("Unknown clock index %d to get max phase\n", ind));
return -1;
}
int ret = ((double)PLL_VCO_FREQ_MHZ / (double)clkDivider[ind]) * MAX_PHASE_SHIFTS_STEPS;
char clock_names[4][10]={"run_clk","adc_clk", "sync_clk", "dbit_clk"};
char* clock_names[] = {CLK_NAMES};
FILE_LOG(logDEBUG1, ("Max Phase Shift (%s): %d (Clock: %d MHz, VCO:%d MHz)\n",
clock_names[ind], ret, clkDivider[ind], PLL_VCO_FREQ_MHZ));
return ret;
}
int validatePhaseinDegrees(enum speedVariable ind, int val, int retval) {
if (val == -1)
return OK;
enum CLKINDEX clkIndex;
switch(ind) {
case ADC_PHASE:
clkIndex = ADC_CLK;
break;
case DBIT_PHASE:
clkIndex = DBIT_CLK;
break;
default:
FILE_LOG(logERROR, ("Unknown speed enum %d for validating phase in degrees\n", (int)ind));
int validatePhaseinDegrees(enum CLKINDEX ind, int val, int retval) {
if (ind != ADC_CLK && ind != DBIT_CLK) {
FILE_LOG(logERROR, ("Unknown clock index %d to validate phase in degrees\n", ind));
return FAIL;
}
FILE_LOG(logDEBUG1, ("validating phase in degrees for clk %d\n", clkIndex));
int maxShift = getMaxPhase(clkIndex);
// convert degrees to shift
if (val == -1) {
return OK;
}
FILE_LOG(logDEBUG1, ("validating phase in degrees for clk %d\n", ind));
int maxShift = getMaxPhase(ind);
// convert degrees to shift
int valShift = 0;
ConvertToDifferentRange(0, 359, 0, maxShift - 1, val, &valShift);
@ -1706,17 +1647,21 @@ int validatePhaseinDegrees(enum speedVariable ind, int val, int retval) {
return FAIL;
}
void configureFrequency(enum CLKINDEX ind, int val) {
char clock_names[4][10]={"run_clk","adc_clk", "sync_clk", "dbit_clk"};
if (val <= 0)
return;
FILE_LOG(logINFO, ("\tConfiguring Frequency of C%d(%s) to %d MHz\n", ind, clock_names[ind], val));
int setFrequency(enum CLKINDEX ind, int val) {
if (ind < 0 || ind >= NUM_CLOCKS) {
FILE_LOG(logERROR, ("Unknown clock index %d to set frequency\n", ind));
return FAIL;
}
if (val <= 0) {
return FAIL;
}
char* clock_names[] = {CLK_NAMES};
FILE_LOG(logINFO, ("\tSetting %s clock (%d) frequency to %d MHz\n", clock_names[ind], ind, val));
// check adc clk too high
if (ind == ADC_CLK && val > MAXIMUM_ADC_CLK) {
FILE_LOG(logERROR, ("Frequency %d MHz too high for ADC\n", val));
return;
return FAIL;
}
// Remembering adcphase/ dbit phase
@ -1727,7 +1672,7 @@ void configureFrequency(enum CLKINDEX ind, int val) {
// Calculate and set output frequency
clkDivider[ind] = ALTERA_PLL_SetOuputFrequency (ind, PLL_VCO_FREQ_MHZ, val);
FILE_LOG(logINFO, ("\tC%d(%s): Frequency set to %d MHz\n", ind, clock_names[ind], clkDivider[ind]));
FILE_LOG(logINFO, ("\t%s clock (%d) frequency set to %d MHz\n", clock_names[ind], ind, clkDivider[ind]));
// adc and dbit phase is reset by pll (when setting output frequency)
clkPhase[ADC_CLK] = 0;
@ -1736,23 +1681,32 @@ void configureFrequency(enum CLKINDEX ind, int val) {
// set the phase if custom set
if (clkPhase[ADC_CLK] != adcPhase) {
FILE_LOG(logINFO, ("\tPhase reset by PLL\n\tCorrecting ADC phase to %d\n", adcPhase));
configurePhase(ADC_CLK, adcPhase, 0);
setPhase(ADC_CLK, adcPhase, 0);
}
if (clkPhase[DBIT_CLK] != dbitPhase) {
FILE_LOG(logINFO, ("\tPhase reset by PLL\n\tCorrecting DBIT phase to %d\n", dbitPhase));
configurePhase(DBIT_CLK, dbitPhase, 0);
setPhase(DBIT_CLK, dbitPhase, 0);
}
// required to reconfigure as adc clock is stopped temporarily when resetting pll (in changing output frequency)
AD9257_Configure();
if (ind != SYNC_CLK) {
configureSyncFrequency(ind);
}
return OK;
}
int getFrequency(enum CLKINDEX ind) {
if (ind < 0 || ind >= NUM_CLOCKS) {
FILE_LOG(logERROR, ("Unknown clock index %d to get frequency\n", ind));
return -1;
}
return clkDivider[ind];
}
void configureSyncFrequency(enum CLKINDEX ind) {
char clock_names[4][10]={"run_clk","adc_clk", "sync_clk", "dbit_clk"};
char* clock_names[] = {CLK_NAMES};
int clka = 0, clkb = 0;
switch(ind) {
case ADC_CLK:
@ -1768,6 +1722,7 @@ void configureSyncFrequency(enum CLKINDEX ind) {
clkb = ADC_CLK;
break;
default:
FILE_LOG(logERROR, ("Unknown clock index %d to configure sync frequcny\n", ind));
return;
}
@ -1798,17 +1753,22 @@ void configureSyncFrequency(enum CLKINDEX ind) {
// configure sync to current
if (configure)
configureFrequency(SYNC_CLK, min);
setFrequency(SYNC_CLK, min);
}
void setAdcOffsetRegister(int adc, int val) {
if (val < 0)
void setPipeline(enum CLKINDEX ind, int val) {
if (ind != ADC_CLK && ind != DBIT_CLK) {
FILE_LOG(logERROR, ("Unknown clock index %d to set pipeline\n", ind));
return;
}
if (val < 0) {
return;
FILE_LOG(logINFO, ("Setting %s Pipeline to %d\n", (adc ? "ADC" : "Dbit"), val));
}
char* clock_names[] = {CLK_NAMES};
FILE_LOG(logINFO, ("Setting %s clock (%d) Pipeline to %d\n", clock_names[ind], ind, val));
uint32_t offset = ADC_OFFSET_ADC_PPLN_OFST;
uint32_t mask = ADC_OFFSET_ADC_PPLN_MSK;
if (!adc) {
if (ind == DBIT_CLK) {
offset = ADC_OFFSET_DBT_PPLN_OFST;
mask = ADC_OFFSET_DBT_PPLN_MSK;
}
@ -1818,13 +1778,18 @@ void setAdcOffsetRegister(int adc, int val) {
bus_w(addr, bus_r(addr) & ~ mask);
// set value
bus_w(addr, bus_r(addr) | ((val << offset) & mask));
FILE_LOG(logDEBUG1, (" %s Offset: 0x%8x\n", (adc ? "ADC" : "Dbit"), bus_r(addr)));
FILE_LOG(logDEBUG1, (" %s clock (%d) Offset: 0x%8x\n", clock_names[ind], ind, bus_r(addr)));
}
int getAdcOffsetRegister(int adc) {
if (adc)
return ((bus_r(ADC_OFFSET_REG) & ADC_OFFSET_ADC_PPLN_MSK) >> ADC_OFFSET_ADC_PPLN_OFST);
return ((bus_r(ADC_OFFSET_REG) & ADC_OFFSET_DBT_PPLN_MSK) >> ADC_OFFSET_DBT_PPLN_OFST);
int getPipeline(enum CLKINDEX ind) {
if (ind != ADC_CLK && ind != DBIT_CLK) {
FILE_LOG(logERROR, ("Unknown clock index %d to get pipeline\n", ind));
return -1;
}
if (ind == DBIT_CLK) {
return ((bus_r(ADC_OFFSET_REG) & ADC_OFFSET_DBT_PPLN_MSK) >> ADC_OFFSET_DBT_PPLN_OFST);
}
return ((bus_r(ADC_OFFSET_REG) & ADC_OFFSET_ADC_PPLN_MSK) >> ADC_OFFSET_ADC_PPLN_OFST);
}

3
slsDetectorServers/ctbDetectorServer/slsDetectorServer_defs.h
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@ -23,11 +23,12 @@ typedef struct ip_header_struct {
} ip_header;
/* Enums */
enum CLKINDEX {RUN_CLK, ADC_CLK, SYNC_CLK, DBIT_CLK, NUM_CLOCKS};
enum ADCINDEX {V_PWR_IO, V_PWR_A, V_PWR_B, V_PWR_C, V_PWR_D, I_PWR_IO, I_PWR_A, I_PWR_B, I_PWR_C, I_PWR_D};
enum DACINDEX {D0, D1, D2, D3, D4, D5, D6, D7, D8, D9,
D10, D11, D12, D13, D14, D15, D16, D17,
D_PWR_D, D_PWR_CHIP, D_PWR_C, D_PWR_B, D_PWR_A, D_PWR_IO};
enum CLKINDEX {RUN_CLK, ADC_CLK, SYNC_CLK, DBIT_CLK, NUM_CLOCKS};
#define CLK_NAMES "run", "adc", "sync", "dbit"
/* Hardware Definitions */
#define NCHAN (36)

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slsDetectorServers/eigerDetectorServer/bin/eigerDetectorServer_developer
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slsDetectorServers/eigerDetectorServer/slsDetectorFunctionList.c
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@ -450,7 +450,7 @@ void setupDetector() {
setParallelMode(DEFAULT_PARALLEL_MODE);
setOverFlowMode(DEFAULT_READOUT_STOREINRAM_MODE);
setStoreInRamMode(DEFAULT_READOUT_OVERFLOW32_MODE);
setSpeed(CLOCK_DIVIDER, DEFAULT_CLK_SPEED);//clk_devider,half speed
setClockDivider(RUN_CLK, DEFAULT_CLK_SPEED);//clk_devider,half speed
setIODelay(DEFAULT_IO_DELAY);
setTiming(DEFAULT_TIMING_MODE);
setStartingFrameNumber(DEFAULT_STARTING_FRAME_NUMBER);
@ -532,25 +532,6 @@ int setDynamicRange(int dr) {
/* parameters - readout */
void setSpeed(enum speedVariable ind, int val) {
if (ind != CLOCK_DIVIDER)
return;
if (val != -1) {
FILE_LOG(logDEBUG1, ("Setting Read out Speed: %d\n", val));
#ifndef VIRTUAL
if (Feb_Control_SetReadoutSpeed(val))
#endif
eiger_readoutspeed = val;
}
}
int getSpeed(enum speedVariable ind) {
if (ind != CLOCK_DIVIDER)
return -1;
return eiger_readoutspeed;
}
int setParallelMode(int mode) {
mode = (mode == 0 ? E_NON_PARALLEL : E_PARALLEL);
#ifndef VIRTUAL
@ -1354,6 +1335,27 @@ int enableTenGigabitEthernet(int val) {
/* eiger specific - iodelay, pulse, rate, temp, activate, delay nw parameter */
int setClockDivider(enum CLKINDEX ind, int val) {
if (ind != RUN_CLK) {
FILE_LOG(logERROR, ("Unknown clock index: %d\n", ind));
return FAIL;
}
if (val >= 0) {
FILE_LOG(logINFO, ("Setting Read out Speed: %d\n", val));
#ifndef VIRTUAL
if (Feb_Control_SetReadoutSpeed(val))
#endif
eiger_readoutspeed = val;
}
}
int getClockDivider(enum CLKINDEX ind) {
if (ind != RUN_CLK) {
FILE_LOG(logERROR, ("Unknown clock index: %d\n", ind));
return FAIL;
}
return eiger_readoutspeed;
}
int setIODelay(int val) {
if (val!=-1) {

4
slsDetectorServers/eigerDetectorServer/slsDetectorServer_defs.h
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@ -30,7 +30,9 @@ enum DACINDEX {E_SVP,E_VTR,E_VRF,E_VRS,E_SVN,E_VTGSTV,E_VCMP_LL,E_VCMP_L
};
enum ADCINDEX {TEMP_FPGAEXT, TEMP_10GE, TEMP_DCDC, TEMP_SODL, TEMP_SODR, TEMP_FPGA, TEMP_FPGAFEBL, TEMP_FPGAFEBR};
enum NETWORKINDEX {TXN_LEFT, TXN_RIGHT, TXN_FRAME,FLOWCTRL_10G};
enum {E_PARALLEL, E_NON_PARALLEL};
enum ROINDEX {E_PARALLEL, E_NON_PARALLEL};
enum CLKINDEX {RUN_CLK, NUM_CLOCKS};
#define CLK_NAMES "run"
/* Hardware Definitions */
#define NCHAN (256 * 256)

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slsDetectorServers/gotthard2DetectorServer/bin/gotthard2DetectorServer_developer
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slsDetectorServers/gotthard2DetectorServer/slsDetectorFunctionList.c
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@ -666,11 +666,25 @@ void calcChecksum(udp_header* udp) {
}
// Detector Specific
int setPhase(enum CLKINDEX ind, int val, int degrees) {
char clock_names[6][15]={"Readout_c0", "Readout_c1", "System_c0", "System_c1", "System_c2", "System_c3"};
FILE_LOG(logDEBUG1, ("\tConfiguring Phase of C%d(%s) to %d (degree mode: %d)\n", ind, clock_names[ind], val, degrees));
if (ind < 0 || ind >= NUM_CLOCKS) {
FILE_LOG(logERROR, ("Unknown clock index %d to set phase\n", ind));
return FAIL;
}
char* clock_names[] = {CLK_NAMES};
FILE_LOG(logINFO, ("Setting %s clock (%d) phase to %d %s\n", clock_names[ind], ind, val, degrees == 0 ? "" : "degrees"));
int maxShift = getMaxPhase(ind);
// validation
if (degrees && (val < 0 || val > 359)) {
FILE_LOG(logERROR, ("\tPhase outside limits (0 - 359°C)\n"));
return FAIL;
}
if (!degrees && (val < 0 || val > maxShift - 1)) {
FILE_LOG(logERROR, ("\tPhase outside limits (0 - %d phase shifts)\n", maxShift - 1));
return FAIL;
}
int valShift = val;
// convert to phase shift
if (degrees) {
@ -686,7 +700,7 @@ int setPhase(enum CLKINDEX ind, int val, int degrees) {
FILE_LOG(logINFO, ("\tNothing to do in Phase Shift\n"));
return OK;
}
FILE_LOG(logINFOBLUE, ("\tConfiguring Phase of C%d(%s) to %d (degree mode: %d)\n", ind, clock_names[ind], val, degrees));
FILE_LOG(logINFOBLUE, ("Configuring Phase\n"));
int phase = 0;
if (relativePhase > 0) {
@ -705,6 +719,10 @@ int setPhase(enum CLKINDEX ind, int val, int degrees) {
}
int getPhase(enum CLKINDEX ind, int degrees) {
if (ind < 0 || ind >= NUM_CLOCKS) {
FILE_LOG(logERROR, ("Unknown clock index %d to get phase\n", ind));
return -1;
}
if (!degrees)
return clkPhase[ind];
// convert back to degrees
@ -714,11 +732,15 @@ int getPhase(enum CLKINDEX ind, int degrees) {
}
int getMaxPhase(enum CLKINDEX ind) {
if (ind < 0 || ind >= NUM_CLOCKS) {
FILE_LOG(logERROR, ("Unknown clock index %d to get max phase\n", ind));
return -1;
}
int vcofreq = getVCOFrequency(ind);
int maxshiftstep = ALTERA_PLL_C10_GetMaxPhaseShiftStepsofVCO();
int ret = ((double)vcofreq / (double)clkDivider[ind]) * maxshiftstep;
char clock_names[6][15]={"Readout_c0", "Readout_c1", "System_c0", "System_c1", "System_c2", "System_c3"};
char* clock_names[] = {CLK_NAMES};
FILE_LOG(logDEBUG1, ("\tMax Phase Shift (%s): %d (Clock: %d Hz, VCO:%d Hz)\n",
clock_names[ind], ret, clkDivider[ind], vcofreq));
@ -726,12 +748,16 @@ int getMaxPhase(enum CLKINDEX ind) {
}
int validatePhaseinDegrees(enum CLKINDEX ind, int val, int retval) {
if (val == -1)
if (ind < 0 || ind >= NUM_CLOCKS) {
FILE_LOG(logERROR, ("Unknown clock index %d to validate phase in degrees\n", ind));
return FAIL;
}
if (val == -1) {
return OK;
}
FILE_LOG(logDEBUG1, ("validating phase in degrees for clk %d\n", (int)ind));
int maxShift = getMaxPhase(ind);
// convert degrees to shift
// convert degrees to shift
int valShift = 0;
ConvertToDifferentRange(0, 359, 0, maxShift - 1, val, &valShift);
// convert back to degrees
@ -745,10 +771,18 @@ int validatePhaseinDegrees(enum CLKINDEX ind, int val, int retval) {
int getFrequency(enum CLKINDEX ind) {
if (ind < 0 || ind >= NUM_CLOCKS) {
FILE_LOG(logERROR, ("Unknown clock index %d to get frequency\n", ind));
return -1;
}
return clkDivider[ind];
}
int getVCOFrequency(enum CLKINDEX ind) {
if (ind < 0 || ind >= NUM_CLOCKS) {
FILE_LOG(logERROR, ("Unknown clock index %d to get vco frequency\n", ind));
return -1;
}
int pllIndex = ind >= SYSTEM_C0 ? SYSTEM_PLL : READOUT_PLL;
return ALTERA_PLL_C10_GetVCOFrequency(pllIndex);
}
@ -758,13 +792,19 @@ int getMaxClockDivider() {
}
int setClockDivider(enum CLKINDEX ind, int val) {
char clock_names[6][15]={"Readout_c0", "Readout_c1", "System_c0", "System_c1", "System_c2", "System_c3"};
if (ind < 0 || ind >= NUM_CLOCKS) {
FILE_LOG(logERROR, ("Unknown clock index %d to set clock divider\n", ind));
return FAIL;
}
if (val < 2 || val > getMaxClockDivider()) {
return FAIL;
}
char* clock_names[] = {CLK_NAMES};
int vcofreq = getVCOFrequency(ind);
int currentdiv = vcofreq / clkDivider[ind];
int newfreq = vcofreq / val;
FILE_LOG(logINFO, ("\tConfiguring Click Divider of C%d(%s) from %d (%d Hz) to %d (%d Hz). \n\t(Vcofreq: %d Hz)\n", ind, clock_names[ind], currentdiv, clkDivider[ind], val, newfreq, vcofreq));
FILE_LOG(logINFO, ("\tSetting %s clock (%d) divider from %d (%d Hz) to %d (%d Hz). \n\t(Vcofreq: %d Hz)\n", clock_names[ind], ind, currentdiv, clkDivider[ind], val, newfreq, vcofreq));
// Remembering old phases in degrees
int oldPhases[NUM_CLOCKS];
@ -772,7 +812,7 @@ int setClockDivider(enum CLKINDEX ind, int val) {
int i = 0;
for (i = 0; i < NUM_CLOCKS; ++i) {
oldPhases [i] = getPhase(i, 1);
FILE_LOG(logDEBUG1, ("\tRemembering C%d (%s) phase: %d degrees\n", ind, clock_names, oldPhases[i]));
FILE_LOG(logDEBUG1, ("\tRemembering %s clock (%d) phase: %d degrees\n", clock_names[ind], ind, oldPhases[i]));
}
}
@ -781,7 +821,7 @@ int setClockDivider(enum CLKINDEX ind, int val) {
int clkIndex = ind >= SYSTEM_C0 ? ind - SYSTEM_C0 : ind;
int ret = ALTERA_PLL_C10_SetOuputFrequency (pllIndex, clkIndex, newfreq);
clkDivider[ind] = newfreq;
FILE_LOG(logINFO, ("\tC%d(%s): Clock Divider set to %d (%d Hz)\n", ind, clock_names[ind], val, clkDivider[ind]));
FILE_LOG(logINFO, ("\t%s clock (%d) divider set to %d (%d Hz)\n", clock_names[ind], ind, val, clkDivider[ind]));
// phase is reset by pll (when setting output frequency)
if (ind >= READOUT_C0) {
@ -798,7 +838,7 @@ int setClockDivider(enum CLKINDEX ind, int val) {
{
int i = 0;
for (i = 0; i < NUM_CLOCKS; ++i) {
FILE_LOG(logINFO, ("\tPhase reset by PLL\n\tCorrecting C%d(%s) to %d degrees\n", i, clock_names[i], oldPhases[i]));
FILE_LOG(logINFO, ("\tPhase reset by PLL\n\tCorrecting %s clock (%d) phase to %d degrees\n", clock_names[i], i, oldPhases[i]));
setPhase(i, oldPhases[i], 1);
}
}
@ -806,6 +846,10 @@ int setClockDivider(enum CLKINDEX ind, int val) {
}
int getClockDivider(enum CLKINDEX ind) {
if (ind < 0 || ind >= NUM_CLOCKS) {
FILE_LOG(logERROR, ("Unknown clock index %d to get clock divider\n", ind));
return -1;
}
return (getVCOFrequency(ind) / clkDivider[ind]);
}

1
slsDetectorServers/gotthard2DetectorServer/slsDetectorServer_defs.h
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@ -77,6 +77,7 @@ enum DACINDEX {G2_VREF_H_ADC, /* 0 */ \
1400 /* 15 (700 mV) VCOM_ADC2*/ \
};
enum CLKINDEX {READOUT_C0, READOUT_C1, SYSTEM_C0, SYSTEM_C1, SYSTEM_C2, SYSTEM_C3, NUM_CLOCKS};
#define CLK_NAMES "READOUT_C0", "READOUT_C1", "SYSTEM_C0", "SYSTEM_C1", "SYSTEM_C2", "SYSTEM_C3"
/* Struct Definitions */
typedef struct udp_header_struct {

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slsDetectorServers/gotthardDetectorServer/bin/gotthardDetectorServer_developer
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27
slsDetectorServers/gotthardDetectorServer/slsDetectorFunctionList.c
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@ -783,21 +783,6 @@ ROI getROI() {
return rois;
}
// parameters - readout
void setSpeed(enum speedVariable ind, int val) {
switch(ind) {
case ADC_PHASE:
setPhaseShift(val);
break;
default:
return;
}
}
int getSpeed(enum speedVariable ind) {
// cannot get phase shift
return -1;
}
/* parameters - timer */
void setNumFrames(int64_t val) {
@ -1513,6 +1498,18 @@ int* getDetectorPosition() {
return detPos;
}
/* gotthard specific - adc phase */
int setPhase(enum CLKINDEX ind, int val, int degrees) {
if (ind != ADC_CLK) {
FILE_LOG(logERROR, ("Unknown clock index: %d\n", ind));
return FAIL;
}
if (degrees != 0) {
FILE_LOG(logERROR, ("Cannot set phase in degrees\n"));
return FAIL;
}
setPhaseShift(val);
}
/* aquisition */

3
slsDetectorServers/gotthardDetectorServer/slsDetectorServer_defs.h
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@ -5,6 +5,9 @@
/* Enums */
enum ADCINDEX {TEMP_FPGA, TEMP_ADC};
enum DACINDEX {G_VREF_DS, G_VCASCN_PB, G_VCASCP_PB, G_VOUT_CM, G_VCASC_OUT, G_VIN_CM, G_VREF_COMP, G_IB_TESTC};
enum CLKINDEX {ADC_CLK, NUM_CLOCKS};
#define CLK_NAMES "adc"
#define DEFAULT_DAC_VALS { \
660, /* G_VREF_DS */ \
650, /* G_VCASCN_PB */ \

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slsDetectorServers/jungfrauDetectorServer/bin/jungfrauDetectorServer_developer
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186
slsDetectorServers/jungfrauDetectorServer/slsDetectorFunctionList.c
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@ -431,7 +431,7 @@ void setupDetector() {
bus_w(DAQ_REG, 0x0); /* Only once at server startup */
FILE_LOG(logINFOBLUE, ("Setting Default parameters\n"));
setClockDivider(HALF_SPEED);
setClockDivider(RUN_CLK, HALF_SPEED);
cleanFifos();
resetCore();
@ -452,7 +452,7 @@ void setupDetector() {
setNumAdditionalStorageCells(DEFAULT_NUM_STRG_CLLS);
setStorageCellDelay(DEFAULT_STRG_CLL_DLY);
selectStoragecellStart(DEFAULT_STRG_CLL_STRT);
/*setClockDivider(HALF_SPEED); depends if all the previous stuff works*/
/*setClockDivider(RUN_CLK, HALF_SPEED); depends if all the previous stuff works*/
setTiming(DEFAULT_TIMING_MODE);
setStartingFrameNumber(DEFAULT_STARTING_FRAME_NUMBER);
@ -542,36 +542,6 @@ uint32_t getADCInvertRegister() {
}
/* parameters - speed, readout */
void setSpeed(enum speedVariable ind, int val, int mode) {
switch(ind) {
case CLOCK_DIVIDER:
setClockDivider(val);
break;
case ADC_PHASE:
setAdcPhase(val, mode);
break;
default:
return;
}
}
int getSpeed(enum speedVariable ind, int mode) {
switch(ind) {
case CLOCK_DIVIDER:
return getClockDivider();
case ADC_PHASE:
return getPhase(mode);
case MAX_ADC_PHASE_SHIFT:
return getMaxPhaseShift();
default:
return -1;
}
}
/* parameters - timer */
int selectStoragecellStart(int pos) {
@ -1376,69 +1346,76 @@ void configureASICTimer() {
bus_w(ASIC_CTRL_REG, (bus_r(ASIC_CTRL_REG) & ~ASIC_CTRL_DS_TMR_MSK) | ASIC_CTRL_DS_TMR_VAL);
}
void setClockDivider(int val) {
// setting
if(val >= 0) {
int setClockDivider(enum CLKINDEX ind, int val) {
if (ind != RUN_CLK) {
FILE_LOG(logERROR, ("Unknown clock index %d to set speed\n", ind));
return FAIL;
}
// stop state machine if running
if(runBusy()) {
stopStateMachine();
}
// stop state machine if running
if(runBusy()) {
stopStateMachine();
uint32_t adcOfst = 0;
uint32_t sampleAdcSpeed = 0;
uint32_t adcPhase = 0;
uint32_t config = CONFIG_FULL_SPEED_40MHZ_VAL;
switch(val) {
case FULL_SPEED:
if(isHardwareVersion2()) {
FILE_LOG(logERROR, ("Cannot set full speed. Should not be here\n"));
return FAIL;
}
FILE_LOG(logINFO, ("Setting Full Speed (40 MHz):\n"));
adcOfst = ADC_OFST_FULL_SPEED_VAL;
sampleAdcSpeed = SAMPLE_ADC_FULL_SPEED;
adcPhase = ADC_PHASE_FULL_SPEED;
config = CONFIG_FULL_SPEED_40MHZ_VAL;
break;
case HALF_SPEED:
FILE_LOG(logINFO, ("Setting Half Speed (20 MHz):\n"));
adcOfst = isHardwareVersion2() ? ADC_OFST_HALF_SPEED_BOARD2_VAL : ADC_OFST_HALF_SPEED_VAL;
sampleAdcSpeed = isHardwareVersion2() ? SAMPLE_ADC_HALF_SPEED_BOARD2 : SAMPLE_ADC_HALF_SPEED;
adcPhase = isHardwareVersion2() ? ADC_PHASE_HALF_SPEED_BOARD2 : ADC_PHASE_HALF_SPEED;
config = CONFIG_HALF_SPEED_20MHZ_VAL;
break;
case QUARTER_SPEED:
FILE_LOG(logINFO, ("Setting Half Speed (10 MHz):\n"));
adcOfst = isHardwareVersion2() ? ADC_OFST_QUARTER_SPEED_BOARD2_VAL : ADC_OFST_QUARTER_SPEED_VAL;
sampleAdcSpeed = isHardwareVersion2() ? SAMPLE_ADC_QUARTER_SPEED_BOARD2 : SAMPLE_ADC_QUARTER_SPEED;
adcPhase = isHardwareVersion2() ? ADC_PHASE_QUARTER_SPEED_BOARD2 : ADC_PHASE_QUARTER_SPEED;
config = CONFIG_QUARTER_SPEED_10MHZ_VAL;
break;
default:
FILE_LOG(logERROR, ("Unknown speed val %d\n", val));
return FAIL;
}
uint32_t adcOfst = 0;
uint32_t sampleAdcSpeed = 0;
uint32_t adcPhase = 0;
uint32_t config = CONFIG_FULL_SPEED_40MHZ_VAL;
bus_w(CONFIG_REG, (bus_r(CONFIG_REG) & ~CONFIG_READOUT_SPEED_MSK) | config);
FILE_LOG(logINFO, ("\tSet Config Reg to 0x%x\n", bus_r(CONFIG_REG)));
switch(val) {
bus_w(ADC_OFST_REG, adcOfst);
FILE_LOG(logINFO, ("\tSet ADC Ofst Reg to 0x%x\n", bus_r(ADC_OFST_REG)));
case FULL_SPEED:
if(isHardwareVersion2()) {
FILE_LOG(logERROR, ("Cannot set full speed. Should not be here\n"));
return;
}
FILE_LOG(logINFO, ("Setting Full Speed (40 MHz):\n"));
adcOfst = ADC_OFST_FULL_SPEED_VAL;
sampleAdcSpeed = SAMPLE_ADC_FULL_SPEED;
adcPhase = ADC_PHASE_FULL_SPEED;
config = CONFIG_FULL_SPEED_40MHZ_VAL;
break;
case HALF_SPEED:
FILE_LOG(logINFO, ("Setting Half Speed (20 MHz):\n"));
adcOfst = isHardwareVersion2() ? ADC_OFST_HALF_SPEED_BOARD2_VAL : ADC_OFST_HALF_SPEED_VAL;
sampleAdcSpeed = isHardwareVersion2() ? SAMPLE_ADC_HALF_SPEED_BOARD2 : SAMPLE_ADC_HALF_SPEED;
adcPhase = isHardwareVersion2() ? ADC_PHASE_HALF_SPEED_BOARD2 : ADC_PHASE_HALF_SPEED;
config = CONFIG_HALF_SPEED_20MHZ_VAL;
break;
case QUARTER_SPEED:
FILE_LOG(logINFO, ("Setting Half Speed (10 MHz):\n"));
adcOfst = isHardwareVersion2() ? ADC_OFST_QUARTER_SPEED_BOARD2_VAL : ADC_OFST_QUARTER_SPEED_VAL;
sampleAdcSpeed = isHardwareVersion2() ? SAMPLE_ADC_QUARTER_SPEED_BOARD2 : SAMPLE_ADC_QUARTER_SPEED;
adcPhase = isHardwareVersion2() ? ADC_PHASE_QUARTER_SPEED_BOARD2 : ADC_PHASE_QUARTER_SPEED;
config = CONFIG_QUARTER_SPEED_10MHZ_VAL;
break;
default:
break;
}
bus_w(SAMPLE_REG, sampleAdcSpeed);
FILE_LOG(logINFO, ("\tSet Sample Reg to 0x%x\n", bus_r(SAMPLE_REG)));
bus_w(CONFIG_REG, (bus_r(CONFIG_REG) & ~CONFIG_READOUT_SPEED_MSK) | config);
FILE_LOG(logINFO, ("\tSet Config Reg to 0x%x\n", bus_r(CONFIG_REG)));
bus_w(ADC_OFST_REG, adcOfst);
FILE_LOG(logINFO, ("\tSet ADC Ofst Reg to 0x%x\n", bus_r(ADC_OFST_REG)));
bus_w(SAMPLE_REG, sampleAdcSpeed);
FILE_LOG(logINFO, ("\tSet Sample Reg to 0x%x\n", bus_r(SAMPLE_REG)));
setAdcPhase(adcPhase, 0);
FILE_LOG(logINFO, ("\tSet ADC Phase Reg to %d\n", adcPhase));
}
setPhase(ADC_CLK, adcPhase, 0);
FILE_LOG(logINFO, ("\tSet ADC Phase Reg to %d\n", adcPhase));
return OK;
}
int getClockDivider() {
int getClockDivider(enum CLKINDEX ind) {
if (ind != RUN_CLK) {
FILE_LOG(logERROR, ("Unknown clock index %d to get speed\n", ind));
return -1;
}
u_int32_t speed = bus_r(CONFIG_REG) & CONFIG_READOUT_SPEED_MSK;
switch(speed){
case CONFIG_FULL_SPEED_40MHZ_VAL:
@ -1448,21 +1425,26 @@ int getClockDivider() {
case CONFIG_QUARTER_SPEED_10MHZ_VAL:
return QUARTER_SPEED;
default:
FILE_LOG(logERROR, ("Unknown speed val: %d\n", speed));
return -1;
}
}
void setAdcPhase(int val, int degrees){
int setPhase(enum CLKINDEX ind, int val, int degrees){
if (ind != ADC_CLK) {
FILE_LOG(logERROR, ("Unknown clock index %d to set phase\n", ind));
return FAIL;
}
int maxShift = MAX_PHASE_SHIFTS;
// validation
if (degrees && (val < 0 || val > 359)) {
FILE_LOG(logERROR, ("\tPhase provided outside limits (0 - 359°C)\n"));
return;
return FAIL;
}
if (!degrees && (val < 0 || val > MAX_PHASE_SHIFTS - 1)) {
FILE_LOG(logERROR, ("\tPhase provided outside limits (0 - %d phase shifts)\n", maxShift - 1));
return;
return FAIL;
}
FILE_LOG(logINFO, ("Setting ADC Phase to %d (degree mode: %d)\n", val, degrees));
@ -1479,7 +1461,7 @@ void setAdcPhase(int val, int degrees){
// same phase
if (!relativePhase) {
FILE_LOG(logINFO, ("Nothing to do in Phase Shift\n"));
return;
return OK;
}
int phase = 0;
@ -1495,9 +1477,14 @@ void setAdcPhase(int val, int degrees){
adcPhase = valShift;
alignDeserializer();
return OK;
}
int getPhase(int degrees) {
int getPhase(enum CLKINDEX ind, int degrees) {
if (ind != ADC_CLK) {
FILE_LOG(logERROR, ("Unknown clock index %d to get phase\n", ind));
return -1;
}
if (!degrees)
return adcPhase;
// convert back to degrees
@ -1506,13 +1493,22 @@ int getPhase(int degrees) {
return val;
}
int getMaxPhaseShift() {
int getMaxPhase(enum CLKINDEX ind) {
if (ind != ADC_CLK) {
FILE_LOG(logERROR, ("Unknown clock index %d to get max phase\n", ind));
return -1;
}
return MAX_PHASE_SHIFTS;
}
int validatePhaseinDegrees(int val, int retval) {
if (val == -1)
int validatePhaseinDegrees(enum CLKINDEX ind, int val, int retval) {
if (ind != ADC_CLK) {
FILE_LOG(logERROR, ("Unknown clock index %d to validate phase in degrees\n", ind));
return FAIL;
}
if (val == -1) {
return OK;
}
FILE_LOG(logDEBUG1, ("validating phase in degrees\n"));
int maxShift = MAX_PHASE_SHIFTS;
// convert degrees to shift

2
slsDetectorServers/jungfrauDetectorServer/slsDetectorServer_defs.h
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@ -49,6 +49,8 @@ enum DACINDEX {J_VB_COMP, J_VDD_PROT, J_VIN_COM, J_VREF_PRECH, J_VB_PIXBUF, J
420 /* J_VREF_COMP */ \
};
enum NETWORKINDEX { TXN_FRAME, FLOWCTRL_10G };
enum CLKINDEX {RUN_CLK, ADC_CLK, NUM_CLOCKS};
#define CLK_NAMES "run", "adc"
/* Hardware Definitions */
#define NCHAN (256 * 256)

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slsDetectorServers/mythen3DetectorServer/bin/mythen3DetectorServer_developer
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slsDetectorServers/mythen3DetectorServer/slsDetectorFunctionList.c
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@ -388,14 +388,6 @@ int setDynamicRange(int dr){
/* parameters - speed, readout */
void setSpeed(enum speedVariable ind, int val) {
}
int getSpeed(enum speedVariable ind) {
return -1;
}
void setNumFrames(int64_t val) {
if (val > 0) {
FILE_LOG(logINFO, ("Setting number of frames %lld\n", (long long int)val));

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slsDetectorServers/slsDetectorServer/include/slsDetectorFunctionList.h
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@ -149,16 +149,6 @@ int setExternalSampling(int val);
#endif
// parameters - readout
#if defined(CHIPTESTBOARDD) || defined(MOENCHD) || defined(JUNGFRAUD)
void setSpeed(enum speedVariable ind, int val, int mode);
int getSpeed(enum speedVariable ind, int mode);
#else
#ifndef GOTTHARD2D
void setSpeed(enum speedVariable ind, int val);
int getSpeed(enum speedVariable ind);
#endif
#endif
#ifdef EIGERD
int setParallelMode(int mode);
int getParallelMode();
@ -355,15 +345,15 @@ int powerChip (int on);
// chip test board or moench specific - configure frequency, phase, pll, flashing firmware
#if defined(CHIPTESTBOARDD) || defined(MOENCHD)
void configurePhase(enum CLKINDEX ind, int val, int degrees);
int setPhase(enum CLKINDEX ind, int val, int degrees);
int getPhase(enum CLKINDEX ind, int degrees);
int getMaxPhase(enum CLKINDEX ind);
int validatePhaseinDegrees(enum speedVariable ind, int val, int retval);
void configureFrequency(enum CLKINDEX ind, int val);
int validatePhaseinDegrees(enum CLKINDEX ind, int val, int retval);
int setFrequency(enum CLKINDEX ind, int val);
int getFrequency(enum CLKINDEX ind);
void configureSyncFrequency(enum CLKINDEX ind);
void setAdcOffsetRegister(int adc, int val);
int getAdcOffsetRegister(int adc);
void setPipeline(enum CLKINDEX ind, int val);
int getPipeline(enum CLKINDEX ind);
extern void eraseFlash(); // programfpga.h
extern int startWritingFPGAprogram(FILE** filefp); // programfpga.h
extern void stopWritingFPGAprogram(FILE* filefp); // programfpga.h
@ -390,12 +380,12 @@ void initReadoutConfiguration();
int powerChip (int on);
int autoCompDisable(int on);
void configureASICTimer();
void setClockDivider(int val);
int getClockDivider();
void setAdcPhase(int val, int degrees);
int getPhase(int degrees);
int getMaxPhaseShift();
int validatePhaseinDegrees(int val, int retval);
int setClockDivider(enum CLKINDEX ind, int val);
int getClockDivider(enum CLKINDEX ind);
int setPhase(enum CLKINDEX ind, int val, int degrees);
int getPhase(enum CLKINDEX ind, int degrees);
int getMaxPhase(enum CLKINDEX ind);
int validatePhaseinDegrees(enum CLKINDEX ind, int val, int retval);
int setThresholdTemperature(int val);
int setTemperatureControl(int val);
int setTemperatureEvent(int val);
@ -407,6 +397,8 @@ void alignDeserializer();
// eiger specific - iodelay, pulse, rate, temp, activate, delay nw parameter
#elif EIGERD
int setClockDivider(enum CLKINDEX ind, int val);
int getClockDivider(enum CLKINDEX ind);
int setIODelay(int val);
int setCounterBit(int val);
int pulsePixel(int n, int x, int y);
@ -423,6 +415,10 @@ int getAllTrimbits();
int getBebFPGATemp();
int activate(int enable);
// gotthard specific - adc phase
#elif GOTTHARDD
int setPhase(enum CLKINDEX ind, int val, int degrees);
#elif MYTHEN3D
uint64_t readPatternWord(int addr);
uint64_t writePatternWord(int addr, uint64_t word);
@ -436,7 +432,7 @@ int setPhase(enum CLKINDEX ind, int val, int degrees);
int getPhase(enum CLKINDEX ind, int degrees);
int getMaxPhase(enum CLKINDEX ind);
int validatePhaseinDegrees(enum CLKINDEX ind, int val, int retval);
//int setFrequency(enum CLKINDEX ind, int val);
//void setFrequency(enum CLKINDEX ind, int val);
int getFrequency(enum CLKINDEX ind);
int getVCOFrequency(enum CLKINDEX ind);
int getMaxClockDivider();

6
slsDetectorServers/slsDetectorServer/include/slsDetectorServer_funcs.h
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@ -11,7 +11,6 @@ int printSocketReadError();
void init_detector();
int decode_function(int);
const char* getRetName();
const char* getSpeedName(enum speedVariable ind);
const char* getFunctionName(enum detFuncs func);
void function_table();
void functionNotImplemented();
@ -78,7 +77,6 @@ int get_measurement_time(int);
int set_dynamic_range(int);
int set_roi(int);
int get_roi(int);
int set_speed(int);
int exit_server(int);
int lock_server(int);
int get_last_client_ip(int);
@ -180,4 +178,6 @@ int set_clock_phase(int);
int get_clock_phase(int);
int get_max_clock_phase_shift(int);
int set_clock_divider(int);
int get_clock_divider(int);
int get_clock_divider(int);
int set_pipeline(int);
int get_pipeline(int);

628
slsDetectorServers/slsDetectorServer/src/slsDetectorServer_funcs.c
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@ -114,22 +114,6 @@ const char* getRetName() {
}
}
const char* getSpeedName(enum speedVariable ind) {
switch (ind) {
case CLOCK_DIVIDER: return "clock_divider";
case ADC_CLOCK: return "adc_clock";
case ADC_PHASE: return "adc_phase";
case ADC_PIPELINE: return "adc_pipeline";
case DBIT_CLOCK: return "dbit_clock";
case DBIT_PHASE: return "dbit_phase";
case DBIT_PIPELINE: return "dbit_pipeline";
case MAX_ADC_PHASE_SHIFT: return "max_adc_phase_shift";
case MAX_DBIT_PHASE_SHIFT: return "max_dbit_phase_shift";
case SYNC_CLOCK: return "sync_clock";
default: return "unknown_speed";
}
}
const char* getRunStateName(enum runStatus ind) {
switch (ind) {
case IDLE: return "idle";
@ -200,7 +184,6 @@ const char* getFunctionName(enum detFuncs func) {
case F_SET_DYNAMIC_RANGE: return "F_SET_DYNAMIC_RANGE";
case F_SET_ROI: return "F_SET_ROI";
case F_GET_ROI: return "F_GET_ROI";
case F_SET_SPEED: return "F_SET_SPEED";
case F_EXIT_SERVER: return "F_EXIT_SERVER";
case F_LOCK_SERVER: return "F_LOCK_SERVER";
case F_GET_LAST_CLIENT_IP: return "F_GET_LAST_CLIENT_IP";
@ -297,7 +280,8 @@ const char* getFunctionName(enum detFuncs func) {
case F_GET_MAX_CLOCK_PHASE_SHIFT: return "F_GET_MAX_CLOCK_PHASE_SHIFT";
case F_SET_CLOCK_DIVIDER: return "F_SET_CLOCK_DIVIDER";
case F_GET_CLOCK_DIVIDER: return "F_GET_CLOCK_DIVIDER";
case F_SET_PIPELINE: return "F_SET_PIPELINE";
case F_GET_PIPELINE: return "F_GET_PIPELINE";
default: return "Unknown Function";
}
@ -359,7 +343,6 @@ void function_table() {
flist[F_SET_DYNAMIC_RANGE] = &set_dynamic_range;
flist[F_SET_ROI] = &set_roi;
flist[F_GET_ROI] = &get_roi;
flist[F_SET_SPEED] = &set_speed;
flist[F_EXIT_SERVER] = &exit_server;
flist[F_LOCK_SERVER] = &lock_server;
flist[F_GET_LAST_CLIENT_IP] = &get_last_client_ip;
@ -456,6 +439,8 @@ void function_table() {
flist[F_GET_MAX_CLOCK_PHASE_SHIFT] = &get_max_clock_phase_shift;
flist[F_SET_CLOCK_DIVIDER] = &set_clock_divider;
flist[F_GET_CLOCK_DIVIDER] = &get_clock_divider;
flist[F_SET_PIPELINE] = &set_pipeline;
flist[F_GET_PIPELINE] = &get_pipeline;
// check
if (NUM_DET_FUNCTIONS >= RECEIVER_ENUM_START) {
@ -2571,131 +2556,6 @@ int get_roi(int file_des) {
return ret;
}
int set_speed(int file_des) {
ret = OK;
memset(mess, 0, sizeof(mess));
int args[3] = {-1, -1, -1};
int retval = -1;
if (receiveData(file_des, args, sizeof(args), INT32) < 0)
return printSocketReadError();
#ifdef GOTTHARD2D
functionNotImplemented();
#else
enum speedVariable ind = args[0];
int val = args[1];
int mode = args[2];
char speedName[20] = {0};
strcpy(speedName, getSpeedName(ind));
FILE_LOG(logDEBUG1, ("Setting speed index %s (speedVariable %d) to %d (mode: %d)\n", speedName, ind, val, mode));
// check index
switch(ind) {
#ifdef JUNGFRAUD
case ADC_PHASE:
case CLOCK_DIVIDER:
case MAX_ADC_PHASE_SHIFT:
#elif CHIPTESTBOARDD
case ADC_PHASE:
case DBIT_PHASE:
case MAX_ADC_PHASE_SHIFT:
case MAX_DBIT_PHASE_SHIFT:
case ADC_CLOCK:
case DBIT_CLOCK:
case SYNC_CLOCK:
case CLOCK_DIVIDER:
case ADC_PIPELINE:
case DBIT_PIPELINE:
#elif MOENCHD
case ADC_PHASE:
case DBIT_PHASE:
case MAX_ADC_PHASE_SHIFT:
case MAX_DBIT_PHASE_SHIFT:
case ADC_CLOCK:
case DBIT_CLOCK:
case SYNC_CLOCK:
case CLOCK_DIVIDER:
case ADC_PIPELINE:
case DBIT_PIPELINE:
#elif GOTTHARDD
case ADC_PHASE:
#elif EIGERD
case CLOCK_DIVIDER:
#endif
break;
default:
modeNotImplemented(speedName, (int)ind);
break;
}
#if (!defined(CHIPTESTBOARDD)) && (!defined(MOENCHD)) && (!defined(JUNGFRAUD))
if (ret == OK && mode == 1) {
ret = FAIL;
strcpy(mess, "deg is not defined for this detector.\n");
FILE_LOG(logERROR,(mess));
}
#endif
#ifdef JUNGFRAUD
if (ret == OK && ind == CLOCK_DIVIDER && val == FULL_SPEED && isHardwareVersion2()) {
ret = FAIL;
strcpy(mess, "Full speed not implemented for this board version.\n");
FILE_LOG(logERROR,(mess));
}
#endif
if (ret == OK) {
// set
if ((val != -1) && (Server_VerifyLock() == OK)) {
#if defined(CHIPTESTBOARDD) || defined(MOENCHD) || defined(JUNGFRAUD)
setSpeed(ind, val, mode);
#else
setSpeed(ind, val);
#endif
}
// get
#if defined(CHIPTESTBOARDD) || defined(MOENCHD) || defined(JUNGFRAUD)
retval = getSpeed(ind, mode);
#else
retval = getSpeed(ind);
#endif
FILE_LOG(logDEBUG1, ("%s: %d (mode:%d)\n", speedName, retval, mode));
// validate
char validateName[20] = {0};
sprintf(validateName, "set %s", speedName);
#ifndef GOTTHARDD
#if defined(CHIPTESTBOARDD) || defined(MOENCHD) || defined(JUNGFRAUD)
if ((ind == ADC_PHASE || ind == DBIT_PHASE) && mode == 1) {
#if defined(CHIPTESTBOARDD) || defined(MOENCHD)
ret = validatePhaseinDegrees(ind, val, retval);
#else
ret = validatePhaseinDegrees(val, retval);
#endif
if (ret == FAIL) {
sprintf(mess, "Could not set %s. Set %d, got %d\n", validateName, val, retval);
FILE_LOG(logERROR,(mess));
}
} else
validate(val, retval, validateName, DEC);
#else
validate(val, retval, validateName, DEC);
#endif
#endif
}
#endif
return Server_SendResult(file_des, INT32, UPDATE, &retval, sizeof(retval));
}
int exit_server(int file_des) {
FILE_LOG(logINFORED, ("Closing Server\n"));
ret = OK;
@ -5463,35 +5323,53 @@ int set_clock_frequency(int file_des) {
if (receiveData(file_des, args, sizeof(args), INT32) < 0)
return printSocketReadError();
FILE_LOG(logINFO, ("Setting frequency of clock %d: %u\n", args[0], args[1]));
FILE_LOG(logDEBUG1, ("Setting clock (%d) frequency : %u\n", args[0], args[1]));
#if !defined(CHIPTESTBOARDD) && !defined(MOENCHD)
functionNotImplemented();
/*
#else
// only set
if (Server_VerifyLock() == OK) {
enum CLKINDEX c = (enum CLKINDEX)args[0];
if (c >= NUM_CLOCKS) {
int ind = args[0];
int val = args[1];
enum CLKINDEX c = 0;
switch (ind) {
case ADC_CLOCK:
c = ADC_CLK;
break;
case DBIT_CLOCK:
c = DBIT_CLK;
break;
case RUN_CLOCK:
c = RUN_CLK;
break;
case SYNC_CLOCK:
ret = FAIL;
sprintf(mess, "Cannot set frequency of clock %d. Max number of clocks is %d.\n", (int)c, NUM_CLOCKS - 1);
FILE_LOG(logERROR, (mess));
} else {
ret = setFrequency(c, args[1]);
if (ret == FAIL) {
strcpy(mess, "Set frequency in unknown state. Reconfigure did not return.\n");
FILE_LOG(logERROR, (mess));
} else {
int retval = getFrequency(c);
FILE_LOG(logDEBUG1, ("retval frequency of clock %d: %d\n", (int)c, retval));
sprintf(mess, "Cannot set sync clock frequency.\n");
FILE_LOG(logERROR,(mess));
break;
default:
modeNotImplemented("clock index (frequency set)", ind);
break;
}
char cval[100];
memset(cval, 0, 100);
sprintf(cval, "set frequency of clock %d Hz", (int)c);
validate(args[1], retval, cval, DEC);
if (ret != FAIL) {
char* clock_names[] = {CLK_NAMES};
char modeName[50] = "";
sprintf(modeName, "%s clock (%d) frequency", clock_names[c], (int)c);
if (getFrequency(c) == val) {
FILE_LOG(logINFO, ("Same %s: %d %s\n", modeName, val, myDetectorType == GOTTHARD2 ? "Hz" : "MHz"));
} else {
setFrequency(c, val);
int retval = getFrequency(c);
FILE_LOG(logDEBUG1, ("retval %s: %d %s\n", modeName, retval, myDetectorType == GOTTHARD2 ? "Hz" : "MHz"));
validate(val, retval, modeName, DEC);
}
}
}
*/
#endif
return Server_SendResult(file_des, INT32, UPDATE, NULL, 0);
}
@ -5504,20 +5382,42 @@ int get_clock_frequency(int file_des) {
if (receiveData(file_des, &arg, sizeof(arg), INT32) < 0)
return printSocketReadError();
FILE_LOG(logDEBUG1, ("Getting frequency of clock %d\n", arg));
FILE_LOG(logDEBUG1, ("Getting clock (%d) frequency\n", arg));
#ifndef GOTTHARD2D
#if !defined(CHIPTESTBOARDD) && !defined(MOENCHD) && !defined(GOTTHARD2D)
functionNotImplemented();
#else
#else
// get only
enum CLKINDEX c = (enum CLKINDEX)arg;
if (c >= NUM_CLOCKS) {
ret = FAIL;
sprintf(mess, "Cannot get frequency of clock %d. Max number of clocks is %d.\n", (int)c, NUM_CLOCKS - 1);
FILE_LOG(logERROR, (mess));
} else {
enum CLKINDEX c = 0;
switch (arg) {
#if defined(CHIPTESTBOARDD) || defined(MOENCHD)
case ADC_CLOCK:
c = ADC_CLK;
break;
case DBIT_CLOCK:
c = DBIT_CLK;
break;
case RUN_CLOCK:
c = RUN_CLK;
break;
case SYNC_CLOCK:
c = SYNC_CLK;
break;
#endif
default:
#ifdef GOTTHARD2D
if (c < NUM_CLOCKS) {
c = (enum CLKINDEX)arg;
break;
}
#endif
modeNotImplemented("clock index (frequency get)", arg);
break;
}
if (ret == OK) {
retval = getFrequency(c);
FILE_LOG(logDEBUG1, ("retval frequency of clock %d Hz: %d\n", (int)c, retval));
char* clock_names[] = {CLK_NAMES};
FILE_LOG(logDEBUG1, ("retval %s clock (%d) frequency: %d %s\n", clock_names[c], (int)c, retval, myDetectorType == GOTTHARD2 ? "Hz" : "MHz"));
}
#endif
return Server_SendResult(file_des, INT32, UPDATE, &retval, sizeof(retval));
@ -5533,51 +5433,86 @@ int set_clock_phase(int file_des) {
if (receiveData(file_des, args, sizeof(args), INT32) < 0)
return printSocketReadError();
FILE_LOG(logINFO, ("Setting phase of clock %d: %u %s\n", args[0], args[1], (args[2] == 0 ? "" : "degrees")));
FILE_LOG(logDEBUG1, ("Setting clock (%d) phase: %u %s\n", args[0], args[1], (args[2] == 0 ? "" : "degrees")));
#ifndef GOTTHARD2D
#if !defined(CHIPTESTBOARDD) && !defined(MOENCHD) && !defined(JUNGFRAUD)&& !defined(GOTTHARDD) && !defined(GOTTHARD2D)
functionNotImplemented();
#else
// only set
if (Server_VerifyLock() == OK) {
enum CLKINDEX c = (enum CLKINDEX)args[0];
if (c >= NUM_CLOCKS) {
ret = FAIL;
sprintf(mess, "Cannot set phase for clock %d. Max number of clocks is %d.\n", (int)c, NUM_CLOCKS - 1);
FILE_LOG(logERROR, (mess));
} else {
int val = args[1];
int degrees = args[2];
if (degrees && (val < 0 || val > 359)) {
ret = FAIL;
sprintf(mess, "Cannot set phase. Phase provided for C%d outside limits (0 - 359°C)\n", (int)c);
FILE_LOG(logERROR, (mess));
} else if (!degrees && (val < 0 || val > getMaxPhase(c) - 1)) {
ret = FAIL;
sprintf(mess, "Cannot set phase. Phase provided for C%d outside limits (0 - %d phase shifts)\n", (int)c, getMaxPhase(c) - 1);
FILE_LOG(logERROR, (mess));
} else {
ret = setPhase(c, val, degrees);
if (ret == FAIL) {
strcpy(mess, "Set phase in unknown state. Reconfigure did not return.\n");
FILE_LOG(logERROR, (mess));
} else {
int retval = getPhase(c, degrees);
FILE_LOG(logDEBUG1, ("retval phase for clock %d: %d %s \n", (int)c, retval, (degrees == 0 ? "" : "degrees")));
int ind = args[0];
int val = args[1];
int inDegrees = args[2] == 0 ? 0 : 1;
enum CLKINDEX c = 0;
switch (ind) {
#if defined(CHIPTESTBOARDD) || defined(MOENCHD) || defined(JUNGFRAUD) || defined(GOTTHARDD)
case ADC_CLOCK:
c = ADC_CLK;
break;
#endif
#if defined(CHIPTESTBOARDD) || defined(MOENCHD)
case DBIT_CLOCK:
c = DBIT_CLK;
break;
#endif
default:
#ifdef GOTTHARD2D
if (c < NUM_CLOCKS) {
c = (enum CLKINDEX)ind;
break;
}
#endif
modeNotImplemented("clock index (phase set)", ind);
break;
}
if (ret != FAIL) {
char* clock_names[] = {CLK_NAMES};
char modeName[50] = "";
sprintf(modeName, "%s clock (%d) phase %s", clock_names[c], (int)c, (inDegrees == 0 ? "" : "(degrees)"));
char cval[100];
memset(cval, 0, 100);
sprintf(cval, "set phase for clock %d",(int)c);
if (!degrees) {
validate(val, retval, cval, DEC);
// gotthard1d doesnt take degrees and cannot get phase
#ifdef GOTTHARDD
if (inDegrees != 0) {
ret = FAIL;
strcpy(mess, "Cannot set phase in degrees for this detector.\n");
FILE_LOG(logERROR, (mess));
}
#else
if (getPhase(c, inDegrees) == val) {
FILE_LOG(logINFO, ("Same %s: %d\n", modeName, val));
} else if (inDegrees && (val < 0 || val > 359)) {
ret = FAIL;
sprintf(mess, "Cannot set %s to %d degrees. Phase outside limits (0 - 359°C)\n", modeName, val);
FILE_LOG(logERROR, (mess));
} else if (!inDegrees && (val < 0 || val > getMaxPhase(c) - 1)) {
ret = FAIL;
sprintf(mess, "Cannot set %s to %d. Phase outside limits (0 - %d phase shifts)\n", modeName, val, getMaxPhase(c) - 1);
FILE_LOG(logERROR, (mess));
}
#endif
else {
int ret = setPhase(c, val, inDegrees);
if (ret == FAIL) {
sprintf(mess, "Could not set %s to %d.\n", modeName, val);
FILE_LOG(logERROR, (mess));
}
// gotthard1d doesnt take degrees and cannot get phase
#ifndef GOTTHARDD
else {
int retval = getPhase(c, inDegrees);
FILE_LOG(logDEBUG1, ("retval %s : %d\n", modeName, retval));
if (!inDegrees) {
validate(val, retval, modeName, DEC);
} else {
ret = validatePhaseinDegrees(c, val, retval);
if (ret == FAIL) {
sprintf(mess, "Could not set %s. Set %d degrees, got %d degrees\n", cval, val, retval);
sprintf(mess, "Could not set %s. Set %d degrees, got %d degrees\n", modeName, val, retval);
FILE_LOG(logERROR,(mess));
}
}
}
#endif
}
}
}
@ -5594,20 +5529,40 @@ int get_clock_phase(int file_des) {
if (receiveData(file_des, args, sizeof(args), INT32) < 0)
return printSocketReadError();
FILE_LOG(logDEBUG1, ("Getting phase for clock %d %s \n", args[0], (args[1] == 0 ? "" : "in degrees")));
FILE_LOG(logDEBUG1, ("Getting clock (%d) phase %s \n", args[0], (args[1] == 0 ? "" : "in degrees")));
#ifndef GOTTHARD2D
#if !defined(CHIPTESTBOARDD) && !defined(MOENCHD) && !defined(JUNGFRAUD) && !defined(GOTTHARD2D)
functionNotImplemented();
#else
// get only
enum CLKINDEX c = (enum CLKINDEX)args[0];
if (c >= NUM_CLOCKS) {
ret = FAIL;
sprintf(mess, "Cannot get phase of clock %d. Max number of clocks is %d.\n", (int)c, NUM_CLOCKS - 1);
FILE_LOG(logERROR, (mess));
} else {
retval = getPhase(c, args[1]);
FILE_LOG(logDEBUG1, ("retval phase for clock %d: %d %s\n", (int)c, retval, (args[1] == 0 ? "" : "degrees")));
int ind = args[0];
int inDegrees = args[1] == 0 ? 0 : 1;
enum CLKINDEX c = 0;
switch (ind) {
#if defined(CHIPTESTBOARDD) || defined(MOENCHD) || defined(JUNGFRAUD)
case ADC_CLOCK:
c = ADC_CLK;
break;
#endif
#if defined(CHIPTESTBOARDD) || defined(MOENCHD)
case DBIT_CLOCK:
c = DBIT_CLK;
break;
#endif
default:
#ifdef GOTTHARD2D
if (c < NUM_CLOCKS) {
c = (enum CLKINDEX)ind;
break;
}
#endif
modeNotImplemented("clock index (phase get)", ind);
break;
}
if (ret == OK) {
retval = getPhase(c, inDegrees);
char* clock_names[] = {CLK_NAMES};
FILE_LOG(logDEBUG1, ("retval %s clock (%d) phase: %d %s\n", clock_names[c], (int)c, retval, (inDegrees == 0 ? "" : "degrees")));
}
#endif
return Server_SendResult(file_des, INT32, UPDATE, &retval, sizeof(retval));
@ -5622,20 +5577,38 @@ int get_max_clock_phase_shift(int file_des) {
if (receiveData(file_des, &arg, sizeof(arg), INT32) < 0)
return printSocketReadError();
FILE_LOG(logDEBUG1, ("Getting max phase shift of clock %d\n", arg));
FILE_LOG(logDEBUG1, ("Getting clock (%d) max phase shift\n", arg));
#ifndef GOTTHARD2D
#if !defined(CHIPTESTBOARDD) && !defined(MOENCHD) && !defined(JUNGFRAUD) && !defined(GOTTHARD2D)
functionNotImplemented();
#else
// get only
enum CLKINDEX c = (enum CLKINDEX)arg;
if (c >= NUM_CLOCKS) {
ret = FAIL;
sprintf(mess, "Cannot get frequency of clock %d. Max number of clocks is %d.\n", (int)c, NUM_CLOCKS - 1);
FILE_LOG(logERROR, (mess));
} else {
retval = getMaxPhase(c);
FILE_LOG(logDEBUG1, ("retval max phase shift of clock %d: %d\n", (int)c, retval));
enum CLKINDEX c = 0;
switch (arg) {
#if defined(CHIPTESTBOARDD) || defined(MOENCHD) || defined(JUNGFRAUD)
case ADC_CLOCK:
c = ADC_CLK;
break;
#endif
#if defined(CHIPTESTBOARDD) || defined(MOENCHD)
case DBIT_CLOCK:
c = DBIT_CLK;
break;
#endif
default:
#ifdef GOTTHARD2D
if (c < NUM_CLOCKS) {
c = (enum CLKINDEX)arg;
break;
}
#endif
modeNotImplemented("clock index (max phase get)", arg);
break;
}
if (ret == OK) {
retval = getMaxPhase(c);
char* clock_names[] = {CLK_NAMES};
FILE_LOG(logDEBUG1, ("retval %s clock (%d) max phase shift: %d\n", clock_names[c], (int)c, retval));
}
#endif
return Server_SendResult(file_des, INT32, UPDATE, &retval, sizeof(retval));
@ -5649,38 +5622,78 @@ int set_clock_divider(int file_des) {
if (receiveData(file_des, args, sizeof(args), INT32) < 0)
return printSocketReadError();
FILE_LOG(logINFO, ("Setting divider of clock %d: %u\n", args[0], args[1]));
FILE_LOG(logDEBUG1, ("Setting clock (%d) divider: %u\n", args[0], args[1]));
#ifndef GOTTHARD2D
#if !defined(EIGERD) && !defined(JUNGFRAUD) && !defined(GOTTHARD2D)
functionNotImplemented();
#else
// only set
if (Server_VerifyLock() == OK) {
enum CLKINDEX c = (enum CLKINDEX)args[0];
int ind = args[0];
int val = args[1];
if (c >= NUM_CLOCKS) {
ret = FAIL;
sprintf(mess, "Cannot set divider of clock %d. Max number of clocks is %d.\n", (int)c, NUM_CLOCKS - 1);
FILE_LOG(logERROR, (mess));
} else if (getClockDivider(c) == val) {
FILE_LOG(logINFO, ("Same clock divider %d\n"));
} else if (val < 2 || val > getMaxClockDivider()) {
ret = FAIL;
sprintf(mess, "Cannot set divider of clock %d to %d. Value should be in range [2-%d]\n", (int)c, val, getMaxClockDivider());
FILE_LOG(logERROR, (mess));
} else {
ret = setClockDivider(c, val);
if (ret == FAIL) {
strcpy(mess, "Set divider in unknown state. Reconfigure did not return.\n");
FILE_LOG(logERROR, (mess));
} else {
int retval = getClockDivider(c);
FILE_LOG(logDEBUG1, ("retval divider of clock %d: %d\n", (int)c, retval));
enum CLKINDEX c = 0;
switch (ind) {
// specific clock index
#if defined(EIGERD) || defined(JUNGFRAUD)
case RUN_CLOCK:
c = RUN_CLK;
break;
#endif
default:
// any clock index
#ifdef GOTTHARD2D
if (c < NUM_CLOCKS) {
c = (enum CLKINDEX)ind;
break;
}
#endif
modeNotImplemented("clock index (divider set)", ind);
break;
}
char cval[100];
memset(cval, 0, 100);
sprintf(cval, "set divider of clock %d Hz", (int)c);
validate(val, retval, cval, DEC);
// validate val range
if (ret != FAIL) {
#ifdef JUNGFRAUD
if (val == (int)FULL_SPEED && isHardwareVersion2()) {
ret = FAIL;
strcpy(mess, "Full speed not implemented for this board version.\n");
FILE_LOG(logERROR,(mess));
} else
#endif
#ifdef GOTTHARD2D
if (val < 2 || val > getMaxClockDivider()) {
char* clock_names[] = {CLK_NAMES};
ret = FAIL;
sprintf(mess, "Cannot set %s clock(%d) to %d. Value should be in range [2-%d]\n", clock_names[c], (int)c, val, getMaxClockDivider());
FILE_LOG(logERROR, (mess));
}
#else
if (val < (int)FULL_SPEED || val > (int)QUARTER_SPEED) {
ret = FAIL;
sprintf(mess, "Cannot set speed to %d. Value should be in range [%d-%d]\n", val, (int)FULL_SPEED, (int)QUARTER_SPEED);
FILE_LOG(logERROR, (mess));
}
#endif
}
if (ret != FAIL) {
char modeName[50] = "speed";
#ifdef GOTTHARD2D
char* clock_names[] = {CLK_NAMES};
sprintf(modeName, "%s clock (%d) divider", clock_names[c], (int)c);
#endif
if (getClockDivider(c) == val) {
FILE_LOG(logINFO, ("Same %s: %d\n", modeName, val));
} else {
int ret = setClockDivider(c, val);
if (ret == FAIL) {
sprintf(mess, "Could not set %s to %d.\n", modeName, val);
FILE_LOG(logERROR, (mess));
} else {
int retval = getClockDivider(c);
FILE_LOG(logDEBUG1, ("retval %s : %d\n", modeName, retval));
validate(val, retval, modeName, DEC);
}
}
}
}
@ -5697,20 +5710,115 @@ int get_clock_divider(int file_des) {
if (receiveData(file_des, &arg, sizeof(arg), INT32) < 0)
return printSocketReadError();
FILE_LOG(logDEBUG1, ("Getting divider of clock %d\n", arg));
FILE_LOG(logDEBUG1, ("Getting clock (%d) divider\n", arg));
#ifndef GOTTHARD2D
#if !defined(EIGERD) && !defined(JUNGFRAUD) && !defined(GOTTHARD2D)
functionNotImplemented();
#else
// get only
enum CLKINDEX c = (enum CLKINDEX)arg;
if (c >= NUM_CLOCKS) {
ret = FAIL;
sprintf(mess, "Cannot get divider of clock %d. Max number of clocks is %d.\n", (int)c, NUM_CLOCKS - 1);
FILE_LOG(logERROR, (mess));
} else {
enum CLKINDEX c = 0;
switch (arg) {
#if defined(EIGERD) || defined(JUNGFRAUD)
case RUN_CLOCK:
c = RUN_CLK;
break;
#endif
default:
#ifdef GOTTHARD2D
if (c < NUM_CLOCKS) {
c = (enum CLKINDEX)arg;
break;
}
#endif
modeNotImplemented("clock index (divider get)", arg);
break;
}
if (ret == OK) {
retval = getClockDivider(c);
FILE_LOG(logDEBUG1, ("retval divider of clock %d Hz: %d\n", (int)c, retval));
char* clock_names[] = {CLK_NAMES};
FILE_LOG(logDEBUG1, ("retval %s clock (%d) divider: %d\n", clock_names[c], (int)c, retval));
}
#endif
return Server_SendResult(file_des, INT32, UPDATE, &retval, sizeof(retval));
}
int set_pipeline(int file_des) {
ret = OK;
memset(mess, 0, sizeof(mess));
int args[2] = {-1, -1};
if (receiveData(file_des, args, sizeof(args), INT32) < 0)
return printSocketReadError();
FILE_LOG(logDEBUG1, ("Setting clock (%d) pipeline : %u\n", args[0], args[1]));
#if !defined(CHIPTESTBOARDD) && !defined(MOENCHD)
functionNotImplemented();
#else
// only set
if (Server_VerifyLock() == OK) {
int ind = args[0];
int val = args[1];
enum CLKINDEX c = 0;
switch (ind) {
case ADC_CLOCK:
c = ADC_CLK;
break;
case DBIT_CLOCK:
c = DBIT_CLK;
break;
default:
modeNotImplemented("clock index (pipeline set)", ind);
break;
}
if (ret != FAIL) {
char* clock_names[] = {CLK_NAMES};
char modeName[50] = "";
sprintf(modeName, "%s clock (%d) piepline", clock_names[c], (int)c);
setPipeline(c, val);
int retval = getPipeline(c);
FILE_LOG(logDEBUG1, ("retval %s: %d\n", modeName, retval));
validate(val, retval, modeName, DEC);
}
}
#endif
return Server_SendResult(file_des, INT32, UPDATE, NULL, 0);
}
int get_pipeline(int file_des) {
ret = OK;
memset(mess, 0, sizeof(mess));
int arg = -1;
int retval = -1;
if (receiveData(file_des, &arg, sizeof(arg), INT32) < 0)
return printSocketReadError();
FILE_LOG(logDEBUG1, ("Getting clock (%d) frequency\n", arg));
#if !defined(CHIPTESTBOARDD) && !defined(MOENCHD)
functionNotImplemented();
#else
// get only
enum CLKINDEX c = 0;
switch (arg) {
case ADC_CLOCK:
c = ADC_CLK;
break;
case DBIT_CLOCK:
c = DBIT_CLK;
break;
default:
modeNotImplemented("clock index (pipeline get)", arg);
break;
}
if (ret == OK) {
retval = getPipeline(c);
char* clock_names[] = {CLK_NAMES};
FILE_LOG(logDEBUG1, ("retval %s clock (%d) pipeline: %d\n", clock_names[c], (int)c, retval));
}
#endif
return Server_SendResult(file_des, INT32, UPDATE, &retval, sizeof(retval));