7 Commits

Include renames

Author	SHA1	Message	Date
maliakal_dandGitHub	8f07d2a464	Dev/xilinx set dac rewrite (#1389) ... * wip * wip * wip. xilinx left * wip. xilinx * wip * wip. compiles * fixed eiger test * more fixes * fixed virtual m3 * fix typos and bugs * setting power to 0 * set power fixed * updated server binaries * minor * refactoring * get vchip refactoring * eiger: unnecessary check for setsettings undefined * retval pointer for printout * eiger.wip, mV in boolean * wip. gotthard2 and m3 * wip. jungfrau * moench.wip * compiles.wip * fix eiger * m3 fix vthresh * fix ctband xilinx * default pwr index = pwr_io * minor:fn name and highvoltage to local var * refactor funcs * minor * minor * check dac voltage only for normal dacs and not for power dacs as the dac voltage range is different for ctb and xilinx ctb, also throw for -1 in set for set_dac in client itself. in the server its not clear if its set or get with a -1 * minor * updated versioning * review changes: removing validateDACValue and other minor stuff * binaries in * wip * refactored m3 vth * minor review * minor review * m3 serverdac index fix * minor	2026-02-23 14:23:13 +01:00
3 people	b4533ac11f	Dev/xilinx ctb test (#942) ... * voltage regulators only looks at dac and not at ctrl_reg * xilinx: change dac max to 2048, setting dac ist not inverse conversion from dac to voltage anymore, but setting power is inverse, also there is max and min to power, a different min for vio and this is checked at funcs interface, not printign or converting to mv in dac for power regulators (as its conversion max and min are different) * Use links for dacs/adc and adapt power rglt thresholds * Remove wait for transceiver reset * adc and dac device not used anymore and hence removed * udp restucturing: arm has to be multiple of 16 and no byteswap in udp_gen, option to compile locally in arm architecture, memsize of the second udp memory has to be limited --------- Co-authored-by: Martin Brückner <martin.brueckner@psi.ch>	2024-08-20 14:33:18 +02:00
maliakal_dandGitHub	3d21bb64c4	Dev/xilinx acq (#901) ... * period and exptime(patternwaittime level 0) * added new regsieterdefs and updated api version and fixedpattern reg * autogenerate commands * formatting * minor * wip resetflow, readout mode, transceiver mask, transceiver enable * acquisition, but streaming done bit and busy (exposing + read chip to fifo) not known yet from fw * programming fpga and device tree done * most configuration done, need to connect configuretransceiver to client * stuck at resetting transciever timed out * minor * fixed virtual, added chip busyto fifo, streaming busy, set/getnext framenumber * configuretransceiver from client, added help in client * make formatt and command generation * tests for xilinx ctb works * command generation * dacs added and tested, power not done * power added * added temp_fpga * binaries in * ctrlreg is 0 to enable chip=fixed, high dac val = min val= fixed, power regulators in weird order=fixed, device tree could be loaded with dacs before adcs=fixed * start works * virtual server sends * receiver works * tests * python function and enum generation, commands generatorn and autocomplete, formatting, tests * tests fail at start(transceiver not aligned) * tests passed * all binaries compiled * eiger binary in * added --nomodule cehck for xilinx	2024-02-07 13:23:08 +01:00
maliakal_d	4de7bb51ed	updated all .h files with license notice and copyright notice	2021-10-14 18:10:56 +02:00
maliakal_d	671cf45fd7	format slsdetectorservers	2020-05-05 15:23:11 +02:00
maliakal_d	cfd3680176	gotthard2 dacs	2019-10-08 17:10:36 +02:00
Marie AndräandDhanya Thattil	5f94b5c246	Dac (#67) ... * dac WIP * dacs WIP * DACs are working with names * namechanges of vrfsh->vshaper, vrfshnpol->vshaperneg * pattern for MY3, configure MAC for MY3	2019-10-07 12:13:25 +02:00