* round CTB clocks to next closest possible value, added freq measurement
* added time for firmware to measrue actual value after frequency change
* add check for backwards compatibility
* change CTB and XCTB clock values to MHz, TODO: units and validation errors
* changed runclk command to use units and float, TODO: dbit, adcclk, why is everything called StringTo ?
* do the same for dbit and adcclk
* added tolerance to exptime, fixed test
* update default values in server defs
* added virtual check in Altera_PLL, update testcases
* change python and pyctbgui to accept and return floating point MHz
* update help and comments
* Dev/ctb clocks fix (#1434)
* introduced new type Hz, typetraits, String conversions, command generation (not yet generated)
* incorrect unit typo
* cmd generation and compiles
* default to MHz, removed space between units for consistency with timers, min and max checks for clks
* in python, but need to change the default to Hz again for clean code and intuition
* allow ints, doubles, implicit conversions
* dont allow raw ints, doubles and implicit conversions
* fixed tests
* added operators for Hz in python
* fix test for min clk for xilinx ctb
* fix test
* fix python tests
* fixed xilinx period and default clks
* test fix
* removed the 3 clock cycle check for ctb and implemented properly the max adc clk frq for altera ctb
* removing 3 clock cycle code from xilinx as well
* formatting
* loadpattern before 3 clk cycles code
* actualtime and measurement time to be implemented in 100ns already in fw
* fix tests
* pyzmq dependency forthe tests
* fixed pyctbgui for freq
* insert tolerance check again
* also added tolerance check for patwaittime
* formatting
* minor: rounding test
* removed Rep redundant in ToString for freq
* intro frequency unit enums, removed unnecessary template behavior for ToString with freq unit, switching from parsing string unit argument to the enum argument for ToString, adding parsing string to unit at CLI boundary
* minor, and binaries
* minor, default clk vals are 0 but set up at detector setup
* get frequency only for that unit
* tolerance process
* missed in previous commit
* some more changes to exptime and validations
* ctb is probably done
* periodleft and delayleft
* fixed xilinx freq conv as well
* fixed m3 bug, binaries
* xilinx: setup also done in stop server so that the clk is not 0
* missed a test marker
* binaries in
* review fixes, simpler validation of timers in ctb and xilinx ctb
* typo fix
* format
* fix tests
---------
Co-authored-by: Martin Mueller <martin.mueller@psi.ch>
Co-authored-by: Dhanya Thattil <dhanya.thattil@psi.ch>
* moench, removed chip version, filter resistor, filter cells, currentsoures, gain mode, setttings(modes), dbitphase, maxdbitphase, autocompdisable, comparatordisabletime, made acq start and stop a pulse, removed unused registers
* added parallel command
* remove gain plot for moench
* moench: updated adc invert val
* moench: update adcoffset to 0xf and adcphase to 140 degrees
* removed sync clock in moench
* updated min fw version
* removing config file in moench server
* copied jungfrau server to moench and adapted
* fixed image size and num packets
* read n rows allows 16
* commneted out configure_asic_timer at server startup. To be removed later the ASIC_CTRL_REG and storage cell options
* moench:removing the decrement (which was in jf) in read n rows to register
* removed lblsamples from gui
