* move hwm into the zmq constructor and reconstruct the socket instead of rebind. seems to work better than rebind (most connections cant bind so fast?)
* fix after merge
* added tests to reconnect zmq sockets when setting rx zmqport and rx zmqhwm, changed the tests scripts a bit to make the receiver starting tcp port configurable
* tests: slsreceiver also starting up with 2000 as default tcp port, using latest cli args for receiver and multi receiver
* releasr notes
---------
Co-authored-by: AliceMazzoleni99 <alice.mazzoleni@psi.ch>
* added fetch fmt server library
* added first draft of matterhorn
* added cpp TCP Interface to slsDetectorServer
* bug: added std::signal for proper handling of ctr+c
* added compile option to set log level
* WIP
* dont use c project settings when building matterhornserver
* updated logger
* WIP
* WIP
* linked fmt to slsProjectOptions
* solved merge conflict
* some refactoring
* cleaned up logs
* WIP
* generated register defs from csv file
* oops given in hex
* properly added fmt as a dependency
* some format changes
* WIP
* used CRTP for virtual detector
* WIP
* added udp functions to matterhornserver
* fixed build
* added Server class usable for all detectors
* removed stopserver
* added some more functions
* wrong overload
* porper cleanup of matterhorn app
* PR Review
* refactored directory structure
* added shared memory for aqcuisition status
* implemented bus read and write
* added Matterhorn data class
* modified memory model
* added SPI communication
* moved memory for Bus communication to BucCommunication class
* WIP added HelperFunction for mask conversion
* completed HelperFunctions
* added tests for MatterHorn Helper Functions
* removed shared memory in destructor
* fixed SPI communication
* moved SharedMemory to slsSupportLib
* added toolchain file for cross compilation
* fix constructor for HarwareSPICommunication is public
* update receiver parameters function
* updated mac address
* uploaded matterhorn server binary tracked as lfs
* small fixes from tests on board
* automatically update matterhorn api version when cross compiling binaries
* fix bug in SPI read
* copy to server_directory/bin when cross compiling
* fixed cmake list
* update generate_registerdefs.py
* fixed copy of server binary
* always return error message
* add error log when opening dev/mem
* code review
* fixed eiger, mythen tests for dynamic range
* second Review
* member function getDerived for better readability
* split code into implementation class and actual class doing tcp communication
* added slsWarnings and c++17 compiler option
* added git lfs to workflow
* fix gitea workflows
* bug: add extra clock register
* implement initial checks
* bug: client excpetcs 4 bytes
* refactoring directory structure and rename to .hpp
* check if detector already set up
* missed .h to .hpp
* Code Review 3
* use temmplate value for stopserver
* use internal CMAKE_CROSSCOMPILING variable
* moved boolean stop server flag to DetectorImpl - moving template parameter up
* missed a file
* replace baseclass:: with this
* add Matterhorn server in github workflow
* whatever workflow bug- lets see
* fixed receiving trim bits changed to int64_t
- changed
- command from `datastream` to `udp_datastream` to be more specific
- Detector API:
- setNumberofUDPInterfaces(pos) =>setNumberofUDPInterfaces() # no position anymore
- getDataStream(portPosition, pos) =>getUDPDataStream(portPosition, pos)
- setDataStream(portPosition, pos) => setUDPDataStream(portPosition) # no position anymore
- modified the dataprocessing thread:
- if gui or call back, start zmq processing (connecting sockets) before starting receiver (disabled ports sends dummy that the client zmq sockets are not ready for)
- if only progress, starting progress processing thread after startReceiver
-
- added
- Detector API:
- getRxDisabledUDPPortIndices()
- getPortPositionList()
- allow disabling/enabling udp interface in receiver for Jungfrua/Moench when both udp interfaces is enabled (This is to go fast, where only one half of the module matters)
- write ports type and disabled ports to master file (tests for it as well)
- tests for python commands as well
- datastream command to deprecated commands
- refactored tests to make the new parameters fit
* first draft of disabling data port at the receiver side. Todo: master file and stream for gui to use
* updated help in command
* formatting
* md5 unchanged
* fix test, check port position for detector type
* wip, udp port enable metadata in client, to:receiver, zmq streaming
* wip, master attributes
* wip, imple=> save only disabled ports with port index, 1 interface, is empty
* works in file. still needs refactoring
* updated writer versions
* udp ports type pass, disabled with api yet
* fixed disabled ports meta data as well
* fixed in developer via other PR
* renamed.more intuitive
* fix in gui that wont wait for disabled ports
* added tests for master file
* extra tests
* move the master fiel tests into its own tests with the disable marker for github tests
* refactoring
* python test
* more intuitive and doc
* release notes
* example for python
* back to before
* minor documentation fix and sending nports unnecessarily for getRxUDPPortDisableMetadata
* doc
* review fixes, 1. using std::array instead of vector, 2. moving udp_datastream command testing with different values into master attributes testing file because we test the master file
* minor
* review: update help
* progress printed before assigned
* try catch inside hdf5
* auto generated code for CLI and formatting
* missing packets should not be checked at github workflow level
* formatting
* improved python doc for udp_datastream help
* indent doc python done
* add rx_restream_stop command. This allows to send a ZMQ dummy header any time user wants to do so. For example this allows to pre-configure the ZMQ processing software before the acquisition begins. Therefore, the dummy header was adapted in order to contain the fields stored in the receiver.
* renamed command, changed inherit, moved commands to zmq related section
* update filename in restreamstop
* renamed helper function, sorted header fields alphabetically
* fixed fnametostream set
* renamed functions, add SetFileName method, format JSON parameters order
* added python bindings and formatting (does nothing really)
* renamed restream stop functions to stream dummy
* checkout .github files from ed8c885
* release notes
---------
Co-authored-by: Dhanya Thattil <dhanya.thattil@psi.ch>
* added fetch fmt server library
* added first draft of matterhorn
* added enum ReturnCode
* added cpp TCP Interface to slsDetectorServer
* added fmt to workflows
* bug: added std::signal for proper handling of ctr+c
* added compile option to set log level
* WIP
* dont use c project settings when building matterhornserver
* updated logger
* WIP
* WIP
* linked fmt to slsProjectOptions
* solved merge conflict
* some refactoring
* cleaned up logs
* added fmt to workflow
* WIP
* generated register defs from csv file
* oops given in hex
* properly added fmt as a dependency
* add fmt to conda recipe
* some format changes
* dont use public headers of fmt
* WIP
* used CRTP for virtual detector
* WIP
* added udp functions to matterhornserver
* Matterhorn in tostring
* warning unused variable from other PR
* fixed build
* updated cmake
* added Server class usable for all detectors
* removed stopserver
* added some more functions
* wrong overload
* porper cleanup of matterhorn app
* PR Review
* refactored directory structure
* used pause insetad of sleep
---------
Co-authored-by: Dhanya Thattil <dhanya.thattil@psi.ch>
* not allowing power names for dac names to prevent duplicate names
* wip
* v_abcd commands should be removed to prevent unintentional usage and throw with a suggestion command for dac and power
* binary in
* dacs with power dac names should work and do not take in dac units to avoid ambiguity, test with 0 value for power dacs should fail, to do: implement power commands
* wip: power in client, tests, and fixed server interfaces and ctb implementation, not tested
* wip. client and xilinx todo
* wip: ctb power works, tests left
* fixed some tests
* added vchip check
* python cmds still left. wip
* fixed xilinx. python left
* wip
* wip. xilinx
* fixed powerchip for ctb
* power all returns all
* configtransceiver is removed
* wip python
* wip
* wip
* wip
* wip
* wip
* wip
* wip xilinx
* wip
* wip
* wip
* pybindings
* fix getdacindex and getdacname for normal detectors to throw if random index that doesnt fit to the detector
* wip
* fixed tests
* fixes for python api
* wip
* python: moved powerlist to Ctb
* fixed tests to work for powelist in Ctb
* moved signallist, adclist, slowadc, slowadclist to Ctb
* throw approperiate error when no modules added for powers
* added dac test
* fix dac default names and test for dacs
* ctb dacs, yet to do othe rdacs
* dacs should work now even in tests
* run all tests
* DetectorPowers->NamedPowers in ctb
* comments
* removed unnecessary test code
* removed hard coded dac names in python NamedDacs and NamedPowers
* minor
* minor
* fixed error messages
* changed power to be able to set DAC directly, using enable and disable methods with enabled to get
* rx_roi fixed when there is no roi for a particular port. Fixed tests for it
* removing todo check if files created because its not enough to count matching pattern file names, but also look at timestamp and create files with timestamp else you read older ones. For now, checking individual rois is enough
* restore md5
---------
Co-authored-by: Erik Fröjdh <erik.frojdh@gmail.com>
* basic ctb config api for register and bit names
* tests for define and definelist pass. yet to implement using them for reg, setbit, clearbit and getbit
* improved autocomplete for getbit,setbit, clearbit
* validate autocomplete
* definelist has no put
* updating help
* converting char array+int in runtimeerror compiles but throws at runtime.Fixed.Tested for it. Also check if string or int before using getregisterdefinitonbyvalue to see if it threw to call the other function. because both of it can throw and we should differentiate the issues for both
* removed std::vector<std::pair<string,int> to std::map<string, int> for defiitions list
* Dev/define cmd tie bit to reg (#1328)
* strong type
* moved everythign to bit_utils class
* pybindings
* added tests for python
* removed duplicates
* removed bit names in reg
* changed BitPosition to BitAddress
* Using define reg/bit from python (#1344)
* define_bit, define_addr in python.
* setBit/clearBit takes int or addr
* added example using bits
* split define into 2 commands define_reg and define_bit, definelist into 2: definelist_reg and definelist_bit
* allow string for register and bit names in c++ api
* refactor from github comments
* naming refactoring (getRegisterDefnition to retunr name and address specifically
* added marker for 8 cmd tests connected to define, changed macro to static constexpr
* changed bitPosition from int to uint32_t
* got rid of setbitposition and setaddress, instead overloaded constructor to take in strings so that the conversion from string to bit address members, takes place within the class for easy maintainance in case type changes
* Removing implicit conversions:
RegisterAddresss and RegisterValue: Removed the implicit conversions.
RegisterAddress: Changed member name from address_ to value_ and method as well to value().
RegisterValue: Also added | operator to be able to concatenate with uint32_t. Same in python bindings (but could not find the tests to modify
* Allowed concatenation with other RegisterValue, made them all constexpr
* fix a ctbConfig test
* Maponstack works with integration tests, but need unit tests
* tests on mapstack
* fixed ctb tests and FixedString being initialized with gibberish
* removing parsing from string inside the class RegisterAddress, BitAddress and RegisterValue
* updated python bindings
* fixed bit utils test
* renaming getRegisterDefintiionAddress/Name=>getRegisterAddress/Name and similary for getBitDefinitionAddress/Name
* updated python bindings
* fix tests (format)
* a few python tests added and python bindings corrected
* replaceing str with __str__ for bit.cpp
* repr reimplemented for bit.cpp
* removed make with registerAddress etc
* starting server for tests per session and nor module
* killprocess throws if no process found-> github runs fails, changed to pkill and not throw
* clean shm shouldnt raise, in ci binary not found
* ignoring these tests for CI, which fail on CI because simulators are not generated in CI. This is in another PR, where it should work
---------
Co-authored-by: Erik Fröjdh <erik.frojdh@gmail.com>
Co-authored-by: froejdh_e <erik.frojdh@psi.ch>
* removed verify, update, fixed getUser to be a free function, generated commands, python bindings yet to do
* python bindings
* fixed tests
* minor
* minor
* format
* slsSupportLib done, at receiver rooting out in implementation
* removed from receiver and client
* removed everywhere except gui, python and client(commands.yaml and Detector.h)
* updated python
* fixed autocomplete to print what the issue is if there is one with ToString when running the autocomplete script to generate fixed.json. updated readme.md in generator folder
* formatting
* removed enums for dacs
* udpating autocomplete and generating commands
* removed gotthard from docs and release notes
* removed dac test
* bug from removing g1
* fixed virtual test for xilinx, was minor. so in this PR
* gui done
* binary in merge fix
* formatting and removing enums
* updated fixed and dump.json
* bash autocomplete
* updated doc on command line generation
* removing increments in dac enums for backward compatibility. Not required
* removed ROI from rxParameters (only in g1), not needed to be backward compatible
* removed the phase shift option from det server staruip
* docs receiver formats rewrite
* added documentation for all the receiver files, updated release notes, udpated help in commands help for timing, fixed by throwing exception for aa dividy by 0 error caused by not freeing memory (detsize) when switching between 1d and 2d detectors, removed unnecessary 'recevier up' printout, fixed dbit list 64 bit mask error in master json file (was not 64 bit before), fixed bug in reading gotthard1 data (needs to be tested)
* generating commands help and formatting, also fix help for trimen command line
* added ctb frame format documentation, added some links to some commands, added documentation about adding expat-devel in installation for rhel8 gui, fixed some indentation issues that screwed up command line help documentation
* added ctb frame format documentation
* updated documentation about zeromq-devel for <8.0.0 versions
* first draft of fixing the free function available within the class
* removed class member function freeSharedmemory for both Detector and Module; made the free function freeSharedmemory accessible to python interface; setHostname if there is already a module in shm will recreate the Detector object while freeing shm completely and keeping detsize and intitialchecks (previous commit), sethostname called from DetectorClass in virtual command to have one point of entry (previous commit), testing Module class frees shared memory using free function
* Detector class: added copy and move constructor and assignmentoperators due to explicit destructor (DetectorImpl fwd declared), DetectorImpl class: included ZmqSocket to remove destructor (should not be virtual in any case), Module class: removed explciit destructor to allow compiler generated constructor and operators
* formatting
* minor fix for readme autocomplete
* updated client version date
* client: stopping a blocking acquire of multi modules checks status to catch slaves that might still be in waiting. Problem is (gotthard2 25um at least) slave is in waiting only temporarily before going go idle/stopped. So a 50ms sleep is necessary ot not throw an unnecessary error
* client: when stopping blocking acquire, wait up to 1s in 50ms increments for slave to stop waiting temporarily
* period and exptime(patternwaittime level 0)
* added new regsieterdefs and updated api version and fixedpattern reg
* autogenerate commands
* formatting
* minor
* wip resetflow, readout mode, transceiver mask, transceiver enable
* acquisition, but streaming done bit and busy (exposing + read chip to fifo) not known yet from fw
* programming fpga and device tree done
* most configuration done, need to connect configuretransceiver to client
* stuck at resetting transciever timed out
* minor
* fixed virtual, added chip busyto fifo, streaming busy, set/getnext framenumber
* configuretransceiver from client, added help in client
* make formatt and command generation
* tests for xilinx ctb works
* command generation
* dacs added and tested, power not done
* power added
* added temp_fpga
* binaries in
* ctrlreg is 0 to enable chip=fixed, high dac val = min val= fixed, power regulators in weird order=fixed, device tree could be loaded with dacs before adcs=fixed
* start works
* virtual server sends
* receiver works
* tests
* python function and enum generation, commands generatorn and autocomplete, formatting, tests
* tests fail at start(transceiver not aligned)
* tests passed
* all binaries compiled
* eiger binary in
* added --nomodule cehck for xilinx
* updated registers, arm64
* compiler set to aarch64 for xilinx server
* updated RegisterDefs.h
* merge into generate branch and resolving conflicts and adding the xilinx changes to callerspecial and commands.yaml
* compiles and can print firmware version (using a different csp0 address)
* fixing other servers (gotthard, jungfrau, moench, mythen3) that it returns in case of mapping failure, xilinxctb: added that it checks type, prints proper fw version, checks kernel date, added armprocessor define to use in common places, added specifiers to supress overflow and truncation warnings
* added detector ip and mac adddress to the printout
* fixed tests and recompiled servers
* if blocking and handling sync, only master gets blocking acq, slaves get non blocking as they are first and so dont get status or error caught when slaves dont get trigger (due to not connected etc) and acq returns with slaves still in waiting status. so check status of all in blocking acq
* for all dets with sync, ensure atleast one master when starting acq
* docs updated about sync
* fix acquisition finished status to have different status for different modules, but does not have to be error. for eg. jf sync fw (2.4.1 gives idle for master and stopped for slaves when stopping acquiistion)
* getVoltageList, getVoltage /set, getMeasuredVoltage, getVoltageNames /set, getVoltageIndex moved to 'Power' as its misleading
* added cstdint and names slowadc, added division to mV
* changed uV to mV in command line slow adc help. removed all python slowadcs (as it was already implemented as slowadc
---------
Co-authored-by: Erik Frojdh <erik.frojdh@gmail.com>
- start acq list: mixup with master pos #743 : fix that only master starts second and not all (for start acq), typo with pos and masters list
- synced master status running when setting to slave #747: synced master status running when setting to slave
