* voltage regulators only looks at dac and not at ctrl_reg
* xilinx: change dac max to 2048, setting dac ist not inverse conversion from dac to voltage anymore, but setting power is inverse, also there is max and min to power, a different min for vio and this is checked at funcs interface, not printign or converting to mv in dac for power regulators (as its conversion max and min are different)
* Use links for dacs/adc and adapt power rglt thresholds
* Remove wait for transceiver reset
* adc and dac device not used anymore and hence removed
* udp restucturing: arm has to be multiple of 16 and no byteswap in udp_gen, option to compile locally in arm architecture, memsize of the second udp memory has to be limited
---------
Co-authored-by: Martin Brückner <martin.brueckner@psi.ch>
* changed common.c readADCFromFile to make it more general and move temperature calculation for Eiger out of this function and inside whereever it is called.
* g2 and m2: gethighvoltage was just a variable set in server, it is now moved to a get inside DAC5671 implementation (but not reading a measured value, instead what is set from a file), high voltage variable used inside DAC5671 for virtual servers
* g2: switching off hv (ifrom non zero to zero value) will wait for 10s; powering on chip reconfigures chip; powering off chip unconfigures chip; powering off chip also includes check if hv = 0, if not throw exception; chip configuration checked before acquring; at start up: hv switched off and chip powered on, so does not wait 10s to switch off hv;
* included test to check powering off chip when hv is on should throw an exception
* g2: check if chip configured before acquiring
* nios: read hv value set from file and virtual still goes into DAC5671 for conversions to and fro dac to V, change common readadc to readparameter to generalize, make sethighvoltage into a get and set to catch errors in get as well, g2: if not at startup, remmeber hv value before setting it and after check if value was being switched off (from a non zero value) and wait 10s if it was (10s wait only for switching off from non zero and not at startup)
* period and exptime(patternwaittime level 0)
* added new regsieterdefs and updated api version and fixedpattern reg
* autogenerate commands
* formatting
* minor
* wip resetflow, readout mode, transceiver mask, transceiver enable
* acquisition, but streaming done bit and busy (exposing + read chip to fifo) not known yet from fw
* programming fpga and device tree done
* most configuration done, need to connect configuretransceiver to client
* stuck at resetting transciever timed out
* minor
* fixed virtual, added chip busyto fifo, streaming busy, set/getnext framenumber
* configuretransceiver from client, added help in client
* make formatt and command generation
* tests for xilinx ctb works
* command generation
* dacs added and tested, power not done
* power added
* added temp_fpga
* binaries in
* ctrlreg is 0 to enable chip=fixed, high dac val = min val= fixed, power regulators in weird order=fixed, device tree could be loaded with dacs before adcs=fixed
* start works
* virtual server sends
* receiver works
* tests
* python function and enum generation, commands generatorn and autocomplete, formatting, tests
* tests fail at start(transceiver not aligned)
* tests passed
* all binaries compiled
* eiger binary in
* added --nomodule cehck for xilinx
* implemented testbus, testfpga, set/get #frames, triggers, allowed that and for connection to client, also allowed, getnumchannels, configuremac, getrunstatus, setdetectorposition with dummy values
* connected kernelversion, hardwareversion, versions, framesl, triggersl, dr, timingmode, pattern (except patioctrl) thats there for altera ctb
* replaced set/get64Bit to set/getU64bit in all loadpattern.c for (ctb and m3 also)
* implemented testbus, testfpga, set/get #frames, triggers, allowed that and for connection to client, also allowed, getnumchannels, configuremac, getrunstatus, setdetectorposition with dummy values
* allowing tests for xilinx
* binaries in
* updated registers, arm64
* compiler set to aarch64 for xilinx server
* updated RegisterDefs.h
* merge into generate branch and resolving conflicts and adding the xilinx changes to callerspecial and commands.yaml
* compiles and can print firmware version (using a different csp0 address)
* fixing other servers (gotthard, jungfrau, moench, mythen3) that it returns in case of mapping failure, xilinxctb: added that it checks type, prints proper fw version, checks kernel date, added armprocessor define to use in common places, added specifiers to supress overflow and truncation warnings
* added detector ip and mac adddress to the printout
* fixed tests and recompiled servers
* draft to fix virtual test when it fails
* catching errors in tests and removing sigchild ignore so servers (process in background) executing commands will not fail (pclose no child processes, if sigchld is ignored) fixed
* uncommented python loading config
* somehow killal slsReciever in second detector test fails even though no receiver running
* fixing script for virtual simlator test:fixed issue with check if process running, fixed moench tests
* moench, removed chip version, filter resistor, filter cells, currentsoures, gain mode, setttings(modes), dbitphase, maxdbitphase, autocompdisable, comparatordisabletime, made acq start and stop a pulse, removed unused registers
* added parallel command
* remove gain plot for moench
* moench: updated adc invert val
* moench: update adcoffset to 0xf and adcphase to 140 degrees
* removed sync clock in moench
* updated min fw version
* removing config file in moench server
* eiger: hardwareversion, fix firmware version unable to read version scenarios, check to see if febl, febr and beb have same fw version
* feb versions can be picked up only after feb initialization
* eiger: adding mask to read/write registers. useful for setting quad parameters as they might have different values for left and right fpga registers.
** fix quad position
* fix quad flipping
* formatting
* copied jungfrau server to moench and adapted
* fixed image size and num packets
* read n rows allows 16
* commneted out configure_asic_timer at server startup. To be removed later the ASIC_CTRL_REG and storage cell options
* moench:removing the decrement (which was in jf) in read n rows to register
* removed lblsamples from gui
- removed getClientServerAPIVersion in server (not used)
- removed rxr side (clientversion compatibility check), removed enum as well as it is now done on the client side.
- versionAPI.h
- GITBRANCH changed to RELEASE
- dates for all API changed to "sem_version date". Scripts to compile servers modified for this. Empty "branch" name will end up with developer for sem_version.
- Version class with constructor taking in the long version (APILIB date). Other member functions including concise(to get sem_version for new releases and date for old releases),
- bypassing initial tests, also now bypasses the client-rxr compatibility check (at rx_hostname command)
- previously, compatibility between client-det was ensuring both had the same detector API (eg. same APIJUNGFRAU)
- Now, compatibility only checks APILIB (client side) and detector API(eg. APIJUNGFRAU) (detector side) have same major version. It only does backward compatibility test. Rest is upto user to ensure.
- If server is from an older release, it will compare dates like previous implementation (APIJUNGFRAU from both client and det)
- - previously, compatibility between client-rxr was ensuring both had the same APIRECEIVER
- Now, compatibility only checks APILIB (client side) and APIRECEIVER (rxr side) have same major version. It only does backward compatibility test. Rest is upto user to ensure.
- If rxr is from an older release, it will compare dates like previous implementation (APIRECEIVER from both client and rxr)
- removed APIGUI, evalVersionVariables.sh, genVersionHeader.sh (not needed or not used)
- clientVersion, rxrversion and detectorserverversion all return strings and not integers (in hex) anymore. Depending if it has semantic versioning, it will print that or the date if it is too old.
- fixed in python (strings for versions)
- check_version function in detector server changed to "initial checks" as it only checks server-firmware compatibility and initial server checks. Client compatibilities are moved to client side.
- --version gives sem_version and date? Is date needed as well. The clientversion, detserverversion and rxrversion API gives only sem_version (no date)
- - formatting
- eiger server: fix for fw workaround where stop acquisition processing done signal does not come up, by removing reset in stop acquisition and waiting for2 seconds for feb done processing signal to go down, if it doesnt, throw if status is not idle.
- error messages not setup for some eiger server errors
- quad fix (chip signals to trim quad, both left and right registers can be different)
- minor logical error of no consequence (stop acquisition returns a different enum than expected)
* g2: new hdi values, write hdi value to reg, set slave/master to reg, able to set master from server config file, server command line and client
* print versions for virtual as well
* separating pattern levels from command name: command line done
* separated patten level from command in examples and default pattern files in servers
* command line and server works
* python: patnloop not verified, wip
* works except for patloop (set, and get does not list properly)
* minor
* fixed tests
* added 3 more levels for ctb and moench
* wip
* minor err msg
* minor
* binaries in
* separating pattern levels from command name: command line done
* separated patten level from command in examples and default pattern files in servers
* command line and server works
* python: patnloop not verified, wip
* works except for patloop (set, and get does not list properly)
* minor
* fixed tests
* added 3 more levels for ctb and moench
* wip
* minor err msg
* minor
* binaries in
* python working
* import fix
* changed fw version for ctb and moench. binaries in
Co-authored-by: Erik Frojdh <erik.frojdh@gmail.com>
* added the possibility to save settings file for m3 and eiger
* added save trimbits to gui
* update release notes
* python wip
* moved location of trimbits save option in gui
* python works
* updating getModule with all its parameters in the server side
* updating binaries
* roi structure expanded to have ymin and ymax
* compile with 'detector roi'
* wip
* wip, rx_roi, rx_clearroi
* wip rxroi
* rxroi wip
* wip rxroi
* merge fix
* wip
* rx_roi works, impl wip, test
* tests in, impl left
* wip, rxroi impl
* wip, rxroi impl
* wip
* setrx_Roi works, getrx_roi, wip
* rx_roi impl done
* wip, rxroi
* wip, getrx_roi rxr ports
* fix ports
* wip
* wip
* fix positions on server side
* wip
* numports wip
* wip
* jungfrau top inner interface row increment
* x, y detpos, wip
* removed eiger row indices flipping in gui (bottom flipping maintained)
* wip
* wip, jungfrau numinterfaces2
* jungfrau virtual works
* eiger, jungfrau, g2 virtual server works
* eiger positions fix, wip
* binaries in
* minor printout
* binaries in
* merge fix
* merge fix
* removing getposition
* setrxroi wip
* set upto port
* get messed, wip
* roi multi to module works, wip
* wip
* roi dont return -1
* added rxroi metadata in master file
* added rxroifromshm, not yet in detector
* rx roi in gui with box, also for gap pixels (gappixels for jungfrau mess)
* fix for segfault in gui with detaching roi box in gui
* wip
* m3 gui: slave timing modes should be discarded when squashing
* fixed m3 virtual data, and fixed counters in gui asthetics
* m3 roi works
* wip, g2
* wip
* handling g225um boards, and showing roi for gainplot as well
* udpate python functions
* fix for 1d and a2d roi written
* fixed actual roi written to file
* no virtual hdf5 when handling rx roi
* test
* minor
* binarie in
* wip, adding m3 functions: polarity, inerpolation, pumpprobe
* added interpol, polarity, pump probe, analog pulsing, digital pulsing
* tests
* binaries in
* update release
* added python polarity enum
* fixed python and minor readability in mythen3.c
* binarie sin
* added all the m3 funcs also in list.c and enablingall counters for enabling interpolation
* binarie sin
