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https://github.com/slsdetectorgroup/slsDetectorPackage.git
synced 2025-06-03 16:40:41 +02:00
eiger server workaround fix for fw stop done signal (#571)
- eiger server: fix for fw workaround where stop acquisition processing done signal does not come up, by removing reset in stop acquisition and waiting for2 seconds for feb done processing signal to go down, if it doesnt, throw if status is not idle. - error messages not setup for some eiger server errors - quad fix (chip signals to trim quad, both left and right registers can be different) - minor logical error of no consequence (stop acquisition returns a different enum than expected)
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@ -107,6 +107,11 @@ This document describes the differences between v7.0.0 and v6.x.x
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- ctb, moench, jungfrau (pll reset at start fixed, before no defines)
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- pybind built into package, no need to update submodule when previous release had different pybind version
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- adcvpp moved from dac.. and api added (ctb, moench)
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- eiger server fix (eiger server: fix for fw workaround where stop acquisition processing done signal does not come up, by removing reset in stop acquisition and waiting for2 seconds for feb done processing signal to go down, if it doesnt, throw if status is not idle.
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error messages not setup for some eiger server errors
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quad fix (chip signals to trim quad, both left and right registers can be different)
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minor logical error of no consequence (stop acquisition returns a different enum than expected))
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-
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2. Resolved Issues
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==================
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@ -690,7 +690,7 @@ int Feb_Control_ProcessingInProgress() {
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unsigned int regr = 0, regl = 0;
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// deactivated should return end of processing
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if (!Feb_Control_activated)
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return IDLE;
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return STATUS_IDLE;
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if (!Feb_Interface_ReadRegister(Feb_Control_rightAddress, FEB_REG_STATUS,
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®r)) {
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@ -704,8 +704,9 @@ int Feb_Control_ProcessingInProgress() {
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"processing status\n"));
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return STATUS_ERROR;
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}
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LOG(logDEBUG1, ("regl:0x%x regr:0x%x\n", regl, regr));
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// processing done
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if ((regr | regl) & FEB_REG_STATUS_ACQ_DONE_MSK) {
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if (regr & regl & FEB_REG_STATUS_ACQ_DONE_MSK) {
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return STATUS_IDLE;
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}
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// processing running
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@ -1030,6 +1031,7 @@ int Feb_Control_StopAcquisition() {
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// wait for feb processing to be done
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int is_processing = Feb_Control_ProcessingInProgress();
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int check_error = 0;
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int check_stuck = 0;
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while (is_processing != STATUS_IDLE) {
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usleep(500);
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is_processing = Feb_Control_ProcessingInProgress();
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@ -1041,12 +1043,28 @@ int Feb_Control_StopAcquisition() {
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break;
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check_error++;
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} // reset check_error for next time
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else
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else {
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check_error = 0;
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}
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// check stuck only 2000 times (1s)
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if (is_processing == STATUS_RUNNING) {
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if (check_stuck == 2000) {
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LOG(logERROR, ("Unable to get feb processing done signal\n"));
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// at least it is idle
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if (Feb_Control_AcquisitionInProgress() == STATUS_IDLE) {
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return 1;
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}
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LOG(logERROR, ("Unable to get acquisition done signal\n"));
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return 0;
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}
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check_stuck++;
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} // reset check_stuck for next time
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else {
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check_stuck = 0;
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}
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}
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LOG(logINFO, ("Feb: Processing done (to stop acq)\n"));
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return 0;
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}
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return 1;
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}
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@ -1606,7 +1624,9 @@ int Feb_Control_SetChipSignalsToTrimQuad(int enable) {
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LOG(logINFO, ("%s chip signals to trim quad\n",
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enable ? "Enabling" : "Disabling"));
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unsigned int regval = 0;
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if (!Feb_Control_ReadRegister(DAQ_REG_HRDWRE, ®val)) {
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// right fpga only
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uint32_t righOffset = DAQ_REG_HRDWRE + Feb_Control_rightAddress;
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if (!Feb_Control_ReadRegister(righOffset, ®val)) {
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LOG(logERROR, ("Could not set chip signals to trim quad\n"));
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return 0;
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}
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@ -1616,7 +1636,7 @@ int Feb_Control_SetChipSignalsToTrimQuad(int enable) {
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regval &= ~(DAQ_REG_HRDWRE_PROGRAM_MSK | DAQ_REG_HRDWRE_M8_MSK);
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}
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if (!Feb_Control_WriteRegister(DAQ_REG_HRDWRE, regval)) {
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if (!Feb_Control_WriteRegister(righOffset, regval)) {
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LOG(logERROR, ("Could not set chip signals to trim quad\n"));
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return 0;
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}
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@ -1652,19 +1672,19 @@ int Feb_Control_WriteRegister(uint32_t offset, uint32_t data) {
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int run[2] = {0, 0};
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// both registers
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if (offset < 0x100) {
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if (offset < Feb_Control_leftAddress) {
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run[0] = 1;
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run[1] = 1;
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}
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// right registers only
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else if (offset >= 0x200) {
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else if (offset >= Feb_Control_rightAddress) {
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run[0] = 1;
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actualOffset = offset - 0x200;
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actualOffset = offset - Feb_Control_rightAddress;
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}
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// left registers only
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else {
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run[1] = 1;
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actualOffset = offset - 0x100;
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actualOffset = offset - Feb_Control_leftAddress;
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}
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for (int iloop = 0; iloop < 2; ++iloop) {
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@ -1702,19 +1722,19 @@ int Feb_Control_ReadRegister(uint32_t offset, uint32_t *retval) {
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uint32_t value[2] = {0, 0};
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int run[2] = {0, 0};
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// both registers
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if (offset < 0x100) {
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if (offset < Feb_Control_leftAddress) {
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run[0] = 1;
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run[1] = 1;
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}
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// right registers only
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else if (offset >= 0x200) {
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else if (offset >= Feb_Control_rightAddress) {
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run[0] = 1;
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actualOffset = offset - 0x200;
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actualOffset = offset - Feb_Control_rightAddress;
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}
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// left registers only
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else {
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run[1] = 1;
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actualOffset = offset - 0x100;
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actualOffset = offset - Feb_Control_leftAddress;
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}
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for (int iloop = 0; iloop < 2; ++iloop) {
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@ -1735,11 +1755,11 @@ int Feb_Control_ReadRegister(uint32_t offset, uint32_t *retval) {
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}
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}
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}
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// Inconsistent values
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if (value[0] != value[1]) {
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// Inconsistent values when reading both registers
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if ((run[0] & run[1]) & (value[0] != value[1])) {
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LOG(logERROR,
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("Inconsistent values read from left 0x%x and right 0x%x\n",
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value[0], value[1]));
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("Inconsistent values read from %s 0x%x and %s 0x%x\n",
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side[0], value[0], side[1], value[1]));
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return 0;
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}
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return 1;
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Binary file not shown.
BIN
slsDetectorServers/eigerDetectorServer/bin/eigerDetectorServer_v6.1.2_rc0
Executable file
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slsDetectorServers/eigerDetectorServer/bin/eigerDetectorServer_v6.1.2_rc0
Executable file
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slsDetectorServers/eigerDetectorServer/bin/eigerDetectorServerv6.1.1_patch
Executable file
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slsDetectorServers/eigerDetectorServer/bin/eigerDetectorServerv6.1.1_patch
Executable file
Binary file not shown.
@ -2185,6 +2185,8 @@ int setTrimbits(int *chanregs, char *mess) {
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// if quad, set M8 and PROGRAM manually
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if (!Feb_Control_SetChipSignalsToTrimQuad(1)) {
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sprintf(mess, "Could not set module. Could not enable chip signals to set trimbits\n");
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LOG(logERROR, (mess));
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sharedMemory_unlockLocalLink();
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return FAIL;
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}
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@ -2198,6 +2200,8 @@ int setTrimbits(int *chanregs, char *mess) {
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// if quad, reset M8 and PROGRAM manually
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if (!Feb_Control_SetChipSignalsToTrimQuad(0)) {
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sprintf(mess, "Could not set module. Could not disable chip signals to set trimbits\n");
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LOG(logERROR, (mess));
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sharedMemory_unlockLocalLink();
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return FAIL;
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}
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@ -2208,6 +2212,8 @@ int setTrimbits(int *chanregs, char *mess) {
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// if quad, reset M8 and PROGRAM manually
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if (!Feb_Control_SetChipSignalsToTrimQuad(0)) {
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sprintf(mess, "Could not set module. Could not disable chip signals to set trimbits\n");
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LOG(logERROR, (mess));
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sharedMemory_unlockLocalLink();
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return FAIL;
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}
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@ -2787,7 +2793,7 @@ int stopStateMachine() {
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#else
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sharedMemory_lockLocalLink();
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// sends last frames from fifo and wait for feb processing done
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if ((Feb_Control_StopAcquisition() != STATUS_IDLE)) {
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if (!Feb_Control_StopAcquisition()) {
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LOG(logERROR, ("failed to stop acquisition\n"));
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sharedMemory_unlockLocalLink();
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return FAIL;
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@ -2810,7 +2816,8 @@ int stopStateMachine() {
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// reset feb and beb
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sharedMemory_lockLocalLink();
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Feb_Control_Reset();
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// uncommenting this out as it randomly does not set the processing bit to high
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//Feb_Control_Reset();
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sharedMemory_unlockLocalLink();
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if (!Beb_StopAcquisition()) {
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LOG(logERROR, ("failed to stop acquisition\n"));
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@ -2903,7 +2910,8 @@ void waitForAcquisitionEnd(int *ret, char *mess) {
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sharedMemory_lockLocalLink();
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if (Feb_Control_WaitForFinishedFlag(5000, 1) == STATUS_ERROR) {
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sharedMemory_unlockLocalLink();
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LOG(logERROR, ("Waiting for finished flag\n"));
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strcpy(mess, "Could not wait for finished flag\n");
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LOG(logERROR, (mess));
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*ret = FAIL;
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return;
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}
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@ -2919,6 +2927,7 @@ void waitForAcquisitionEnd(int *ret, char *mess) {
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sharedMemory_unlockLocalLink();
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if (i == STATUS_ERROR) {
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strcpy(mess, "Could not read feb processing done register\n");
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LOG(logERROR, (mess));
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*ret = (int)FAIL;
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return;
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}
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@ -2930,6 +2939,7 @@ void waitForAcquisitionEnd(int *ret, char *mess) {
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// wait for beb to send out all packets
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if (Beb_IsTransmitting(&isTransmitting, send_to_ten_gig, 1) == FAIL) {
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strcpy(mess, "Could not read delay counters\n");
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LOG(logERROR, (mess));
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*ret = (int)FAIL;
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return;
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}
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@ -1527,7 +1527,7 @@ int write_register(int file_des) {
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} else {
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if (readRegister(addr, &retval) == FAIL) {
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ret = FAIL;
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sprintf(mess, "Could not read register 0x%x.\n", addr);
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sprintf(mess, "Could not read register 0x%x or inconsistent values. Try to read +0x100 for only left and +0x200 for only right.\n", addr);
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LOG(logERROR, (mess));
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}
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}
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@ -1565,7 +1565,7 @@ int read_register(int file_des) {
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#elif EIGERD
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if (readRegister(addr, &retval) == FAIL) {
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ret = FAIL;
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sprintf(mess, "Could not read register 0x%x.\n", addr);
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sprintf(mess, "Could not read register 0x%x or inconsistent values. Try +0x100 for only left and +0x200 for only right..\n", addr);
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LOG(logERROR, (mess));
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}
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#else
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@ -10,5 +10,5 @@
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#define APIGOTTHARD2 0x221018
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#define APIJUNGFRAU 0x221018
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#define APIMOENCH 0x221018
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#define APIEIGER 0x221018
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#define APIMYTHEN3 0x221107
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#define APIEIGER 0x221107
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