digital readout mode (fifoempty flag in status register is always up, so it is idle for this readout mode),
pattern loop bugs, max_pattern_length redefined in server side, do not update period for ctb and moench in setreceiver
- allowed flags resetfpga and programfpga for moench and ctb
- set a minimum voltage for vio as it powers the fpga (1200mV)
- changed the min and max for vchip and power regulators due to tolerance
- fixed pattern read function
- fixed minor bugs with input of ctb patterns(waittime) and mode other than 1
- fixed calibration current register for i2c for tolerance (/1.2268)
- fixed current readout of i2c
- added digital, analog and normal readouts for flags
