80b053eb10
binaries resolved, merge conflict from developer
2020-09-10 10:19:34 +02:00
Dhanya Thattil
3cd4f3897b
M3: software trigger ( #175 )
2020-09-10 10:15:45 +02:00
52303daffd
binaries in
2020-09-09 16:44:23 +02:00
a9d1a78662
m3:smp_clk (timing rxr) changed back to clk div 5
2020-09-09 15:55:13 +02:00
3cf2160a2d
binaries in
2020-09-09 15:25:48 +02:00
b33fdf4462
merge conflict fixed and merged with developer
2020-09-09 12:31:36 +02:00
6c8443f09e
binaries in
2020-09-09 12:14:38 +02:00
97687f0f6d
binary in
2020-09-08 17:33:06 +02:00
bfbfe204f4
m3: default clocks changed
2020-09-08 17:31:44 +02:00
87bad38f80
binary in
2020-09-08 15:46:32 +02:00
67f1f9924a
m3:software trigger
2020-09-08 15:45:35 +02:00
e1e04ee755
binaries in
2020-09-08 15:18:07 +02:00
20a959bf61
update mode to skip firmware checks and setupDetector, kernel check added to m3and g2
2020-09-08 15:08:45 +02:00
aecde086a0
binaries in
2020-09-08 12:16:41 +02:00
311cebcd00
m3:added parallel mode
2020-09-08 12:16:02 +02:00
f26d8e514b
merged with g2continuous
2020-09-08 08:46:37 +02:00
0b9ff70244
binaries in
2020-09-08 08:25:24 +02:00
891b8dbd2c
mythen3: wrong hardware version number, so it didnt reboot after programfpga
2020-09-03 17:04:58 +02:00
00978a52c8
added smp_clk, changed rdo vco freq from 1.25GHz to 1GHz, changed rdo clock dividers
2020-09-01 12:06:39 +02:00
bc5cc3fa29
stopping in virtual server needs a usleep before acquiring lock to get status
2020-08-27 18:21:46 +02:00
7ea86dec43
m3 binaries in
2020-08-18 15:28:30 +02:00
eeb386fef5
mythen3: txndelay frame added
2020-08-18 15:27:30 +02:00
27b2a607c8
binaries in
2020-08-10 12:05:37 +02:00
bbf8ab4b88
binary in
2020-08-05 09:49:13 +02:00
321ed13659
merge from developer
2020-08-04 17:43:38 +02:00
f6172f9b9e
binary in
2020-08-04 17:36:49 +02:00
5616d4aeeb
m3: deserializers reg also have to updated when changing dr, #counters
2020-08-04 17:32:34 +02:00
bb3951c201
binaries in
2020-08-04 16:57:06 +02:00
d25f9093d5
binary in
2020-08-04 12:02:37 +02:00
d24edd52e1
m3: optimizing 1g and 10g digitizing by setting number of packets depending on 10/1g, dr and #counters
2020-08-04 12:01:28 +02:00
7b1ede32b1
m3: optimizing 1g and 10g digitizing by setting number of packets depending on 10/1g, dr and #counters
2020-08-04 11:58:20 +02:00
0514f00552
m3: update deserializers except for deserializer reg
2020-08-03 17:23:04 +02:00
Dhanya Thattil
7492f7dbfa
m3: numpackets to 2 or 20 depending on ten giga enable ( #123 )
2020-07-30 15:02:33 +02:00
f358492e09
all binaries in
2020-07-29 16:53:21 +02:00
54ad92a2bf
binarires in
2020-07-29 13:26:55 +02:00
Dhanya Thattil
ad297e9c51
Readlink ( #117 )
...
* gotthard config file path using readlink
* gotthard2
* eiger
* eieger, mnythen3, moench
* binaries in
* moved readlink to a common function
* binaries in
2020-07-23 12:17:46 +02:00
37fc69b297
modified permissions of config file
2020-07-20 18:01:13 +02:00
b46809e1c0
binaries in
2020-07-20 17:36:55 +02:00
28fb1023fa
mythen3: rename default pattern txt and move to inst dir
2020-07-20 17:18:59 +02:00
da2f12072f
virtual data mythen3 fix
2020-07-17 19:19:21 +02:00
918da2402f
binaries in
2020-07-17 19:06:30 +02:00
a76ed6d8db
tengiga enable
2020-07-17 18:34:23 +02:00
b7cb341ee3
dr
2020-07-17 17:33:43 +02:00
546bef5e5a
powerchip at server startup
2020-07-17 15:38:27 +02:00
2d68b61f00
binaries recompiled
2020-07-17 12:59:37 +02:00
ae9499047b
powerpc and nios binaries in
2020-07-16 16:36:49 +02:00
293fda0c7a
mythen3, gotthard2: bug fix- changing wrong pll phases when changing frequency
2020-07-13 15:47:43 +02:00
1e0160d655
updated default pattern
2020-07-08 12:33:33 +02:00
42b7f6fa7c
binary in
2020-07-08 11:35:46 +02:00
4a1943216b
default pattern file for mythen3
2020-07-07 15:50:32 +02:00
