591 Commits

Author SHA1 Message Date
22c2bb0258 eiger: fw 27 fix for delays 2020-09-10 10:26:16 +02:00
80b053eb10 binaries resolved, merge conflict from developer 2020-09-10 10:19:34 +02:00
Dhanya Thattil
3cd4f3897b
M3: software trigger (#175) 2020-09-10 10:15:45 +02:00
52303daffd binaries in 2020-09-09 16:44:23 +02:00
a9d1a78662 m3:smp_clk (timing rxr) changed back to clk div 5 2020-09-09 15:55:13 +02:00
3cf2160a2d binaries in 2020-09-09 15:25:48 +02:00
b33fdf4462 merge conflict fixed and merged with developer 2020-09-09 12:31:36 +02:00
6c8443f09e binaries in 2020-09-09 12:14:38 +02:00
Erik Frojdh
bf52ec10da help printed neutral 2020-09-09 11:06:47 +02:00
bdac4d133e conflict solved and merged with developer 2020-09-09 10:27:14 +02:00
Dhanya Thattil
e8156d412e
G2: continuous internal mode (#167) 2020-09-09 10:13:15 +02:00
97687f0f6d binary in 2020-09-08 17:33:06 +02:00
bfbfe204f4 m3: default clocks changed 2020-09-08 17:31:44 +02:00
87bad38f80 binary in 2020-09-08 15:46:32 +02:00
67f1f9924a m3:software trigger 2020-09-08 15:45:35 +02:00
e1e04ee755 binaries in 2020-09-08 15:18:07 +02:00
6e06d4307d WIP 2020-09-08 15:10:57 +02:00
20a959bf61 update mode to skip firmware checks and setupDetector, kernel check added to m3and g2 2020-09-08 15:08:45 +02:00
aecde086a0 binaries in 2020-09-08 12:16:41 +02:00
311cebcd00 m3:added parallel mode 2020-09-08 12:16:02 +02:00
f26d8e514b merged with g2continuous 2020-09-08 08:46:37 +02:00
0b9ff70244 binaries in 2020-09-08 08:25:24 +02:00
e82e531fb1 server arguments like linux 2020-09-08 08:18:48 +02:00
503f83e8e3 Merge branch 'developer' into g2continuous 2020-09-07 17:07:09 +02:00
f280d033b9 binarie sin 2020-09-07 16:44:48 +02:00
c9cf845c9a WIP 2020-09-07 16:44:26 +02:00
b20720686e gotthard2: changed order of burst mode enums, added a 4th burst mode cw internal burst mode 2020-09-07 16:13:33 +02:00
5b182469a1 rxr: fixed all updates from rxParameters, connected them in masterAttributes, added json header and scan parametes in metadata 2020-09-04 13:49:30 +02:00
891b8dbd2c mythen3: wrong hardware version number, so it didnt reboot after programfpga 2020-09-03 17:04:58 +02:00
d62d5ef804 binaries in 2020-09-02 17:03:19 +02:00
dbaab61ea2 g2: print ns in server before converting to freq 2020-09-02 17:02:12 +02:00
658a804cca gotthard2: change default clock divider of readout clocks 1 and 2 from 8 to 6 2020-09-02 16:48:58 +02:00
00978a52c8 added smp_clk, changed rdo vco freq from 1.25GHz to 1GHz, changed rdo clock dividers 2020-09-01 12:06:39 +02:00
8400c686b5 binaries in 2020-08-31 18:22:41 +02:00
adb6171e35 eiger server: more checks for feb interface reg readouts 2020-08-31 18:22:16 +02:00
973b8f7106 eiger server: more checks for feb interface reg readouts 2020-08-31 18:19:56 +02:00
bc5cc3fa29 stopping in virtual server needs a usleep before acquiring lock to get status 2020-08-27 18:21:46 +02:00
Dhanya Thattil
4e9c99d65d
Merge branch 'developer' into m3txndelay 2020-08-18 15:58:32 +02:00
Dhanya Thattil
dd918fb326
eiger deactivate beb functions (#140)
eiger: some deactivated beb functions should return a value instead of accessng  beb
2020-08-18 15:52:52 +02:00
7ea86dec43 m3 binaries in 2020-08-18 15:28:30 +02:00
eeb386fef5 mythen3: txndelay frame added 2020-08-18 15:27:30 +02:00
0c7759d7e4 formatting 2020-08-11 17:09:36 +02:00
27b2a607c8 binaries in 2020-08-10 12:05:37 +02:00
bbf8ab4b88 binary in 2020-08-05 09:49:13 +02:00
79f010a438 renamed is_configurable to is_udp_configured 2020-08-05 09:37:58 +02:00
321ed13659 merge from developer 2020-08-04 17:43:38 +02:00
f6172f9b9e binary in 2020-08-04 17:36:49 +02:00
5616d4aeeb m3: deserializers reg also have to updated when changing dr, #counters 2020-08-04 17:32:34 +02:00
bb3951c201 binaries in 2020-08-04 16:57:06 +02:00
380b062216 configure mac 2020-08-04 16:55:31 +02:00