Dhanya Thattil
de53747ddd
Counters ( #71 )
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* mythen3: adding counters mask, firmware still takes only number of counters for now
* mythen3: checking if module attached before powering on chip
* bug fix: loop inital declaration not allowed in c
* fix scope eiger test
* mythen3: renamed setCounters to setCounterMask and getCounterMask in API
* mythen3 replacing counting bits with popcount
Co-authored-by: Erik Fröjdh <erik.frojdh@gmail.com>
2020-01-14 17:40:46 +01:00
086cbacd84
mythen3: connected busy signal insttead of timer
2019-12-10 11:03:27 +01:00
9455a5fba1
ctb: adcenable10g included, 10g readout enables included
2019-11-27 17:28:57 +01:00
94382c1ece
m3 and g2: while setting clock freq, change phase only if there is a change in phase (removing more printouts, will still only set if needed )
2019-11-25 10:54:30 +01:00
a95ab1e13e
servers: default compile not update versionign
2019-11-22 17:23:07 +01:00
c4675da0c3
m3: reset fixed
2019-11-22 16:40:43 +01:00
ba008db29a
m3 ang g2: reset not yet imple
2019-11-22 11:54:45 +01:00
d07873ee39
mythen3 and gotthard2: wait request not needed, reset to be implemented
2019-11-22 11:29:24 +01:00
f8df11886a
ctb: change in phase done in degrees (phase reset due to change in frequency)
2019-11-21 15:08:38 +01:00
c4ae32b216
mythen3: setting clk frequecy and phase shifts work
2019-11-21 14:36:37 +01:00
fea94b15d5
mythen3:forgot binary
2019-11-21 13:48:39 +01:00
955bc74a91
mythen3: change vco freq to 1.25GHz
2019-11-21 13:38:54 +01:00
781e8fc67f
mythen3: workaround for busy signal
2019-11-20 11:57:14 +01:00
1cea6af590
mythen3, gotthard2: change phase, change freq bugfix
2019-11-19 17:57:28 +01:00
dfc886a65b
mythen3 gui
2019-11-18 17:57:19 +01:00
206041989f
mythen3, reading dr back fix
2019-11-11 18:33:59 +01:00
2fff9f5bfe
merge
2019-11-11 18:03:13 +01:00
90c34e4942
gotthard2, dacs and onchip dacs from config file
2019-11-11 18:02:08 +01:00
bb26b993ea
servers, firmware check message to init message, minor
2019-11-11 12:00:04 +01:00
Marie Andrae
f53d260202
mythen3: change vph and vpl
2019-11-11 11:40:06 +01:00
2123fb47a5
mythen3: config reg enable all counters, dr
2019-11-11 10:41:42 +01:00
38ad5d7931
mythen3 rxr
2019-11-08 18:11:27 +01:00
a92d931a8f
mythen3 frequency fixes
2019-11-07 14:35:13 +01:00
615b3b2557
WIP
2019-11-06 19:07:00 +01:00
1797d39216
updated mythen3 to configure phase, freq, delay left, period left, actual time, measurement time, framesfrom start and othe register mappings
2019-11-06 18:58:22 +01:00
0f9fd5cd73
rename of clkdivider to clkfrequency in servers
2019-11-06 16:58:34 +01:00
73b5c3ac57
merge
2019-11-06 16:46:00 +01:00
18b8720c17
separated parameters and versions
2019-11-06 16:43:59 +01:00
Marie Andrae
7de9401bc7
powerchip for mythen3
2019-11-06 11:50:09 +01:00
cd5d327988
virtual servers updated
2019-11-06 11:09:48 +01:00
1f64d2a4e2
speed separated
2019-11-05 18:50:35 +01:00
031241ae28
timer split up
2019-11-04 16:40:11 +01:00
f9fff97f8a
mythen3 register mix up
2019-10-31 14:48:53 +01:00
6c5c4f00b3
mythen3 calc checksum
2019-10-31 12:31:51 +01:00
11ea071543
adcinvert for jungfrau, gui for jungfrau dacs
2019-10-30 12:28:51 +01:00
82570bc084
daclist and dacvalues
2019-10-30 11:09:34 +01:00
fe467cdf70
jungfrau dacs named
2019-10-29 18:11:16 +01:00
aa8610fb04
WIP
2019-10-29 10:11:36 +01:00
Dhanya Thattil
995f0924e5
Commandline ( #66 )
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* WIP
* WIP
* removed status to string from defs
* WIP
* WIP
* WIP removed unused functions in multi
* WIP
* print hex in a terrible way
* WIP, loadconfig error
* WIP, type to string
* WIP
* fix to conversion
* WIP, hostname doesnt work
* WIP
* WIP
* WIP
* WIP, threshold
* WIP, threshold
* WIP
* WIP, triggers
* WIP, cycles to triggers
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* rx_udsocksize fx, WIP
* WIP
* WIP
* WIP
* file index (64 bit), WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* merge
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* New python mod
2019-10-21 10:29:06 +02:00
Marie Andrä
9b4fc02b0e
start/stop statemachine for my3 ( #68 )
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* start/stop statemachine for my3
* runStatus, readFrame, runBusy (use CONTROL_REG) for mythen3
* registers for Pavel
* change dac names Mythen3
2019-10-09 13:52:07 +02:00
cfd3680176
gotthard2 dacs
2019-10-08 17:10:36 +02:00
Marie Andrä
5f94b5c246
Dac ( #67 )
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* dac WIP
* dacs WIP
* DACs are working with names
* namechanges of vrfsh->vshaper, vrfshnpol->vshaperneg
* pattern for MY3, configure MAC for MY3
2019-10-07 12:13:25 +02:00
2a40c7f48e
recompiled all servers
2019-09-30 14:54:31 +02:00
Dhanya Thattil
ca054626e6
Removeudpcache ( #65 )
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* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* WIP
* solved eiger 1-10g issue
* some fixes for remove udp cache to work
* bug fix virtual
* removed special handling of rx_udpip
2019-09-30 14:46:25 +02:00
Marie Andrä
6e6fcec698
MY3.0:read and write Registers, frames, cycles, delay ( #64 )
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* MY3.0:read and write Registers, frames, cycles, delay
* write pattern seems to work
* done all corrections. added default clks: run_clk=125MHz, tick_clk=20MHz (fix), sampling_clk=80MHz (from Carlos)
* clk check for aquistition time
* clk check for aquistition time
* Update slsDetectorServer_defs.h
* Update slsDetectorFunctionList.c
2019-09-30 14:36:33 +02:00
Erik Frojdh
27d223d199
testing
2019-09-19 12:12:25 +02:00
Marie Andrä
4b987abf41
Niosmarie ( #63 )
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* HV for Mythen3 server
* HV for mythen3 server
* corrected upstreams
* missing endif
2019-09-03 09:36:02 +02:00
40b62ef5a4
recompiled binaries
2019-09-02 19:31:36 +02:00
cb8c7eea54
updated binaries
2019-08-30 11:26:23 +02:00
Dhanya Thattil
0d35b966ff
Separate headers ( #57 )
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* WIP, ctb
* WIP, eiger
* WIP, gotthard
* WIP, jungfrau
* WIP, gotthard2
* WIP, mythen3
* WIP, moench
* fixed gotthard apiversioning mismatch with gotthard2
2019-08-30 11:17:37 +02:00
